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HIgh speed design

Other Parts Discussed in Thread: ASH

Hi,

We are making validation board and we need to validate the high-speed signals.

The interface flow is like this SOC-->Level translator-->MUX--->End device.

Problem 1 :- Series termination

Where need to put series termination resistor? As from TI article I knew that it should be transmitter side but here my high-speed data signal are bidirectional.

so does it mean that I need the series termination at near soc side(when SOC is transmitting the signal) and at level translator side also (when end device is sending the data). Better understanding I can draw :-

SOC SR(near SOC)-->SR(neat level translator)Level translator(SR near LT)-->MUX(SR near MUX)-->SR(near end device)End device.

I know it is wrong but my data signals are bi-directional?

Problem 2- Where should I need to give test points provisions?As I read, It should be at Receiver side.

When I am receiving the signals from end device then it should be at SOC side(test points)  and when SOC is transmitting the signal it should be at end points(Test Points).But here I have doubt that we are doing validation of SOC so for both TX and RX signals test points should be at SOC side(we are validating the SOC not end device). Can you explain here?

Problem 3-

SOC-->Level translator-->MUX--->End device

Where need to probe the signals, for RX signals it should be near SOC side but for TX signals?Because when SOC is transmitting the level translator is receiver for SOC so should I measure at level translator side?I am Confused. Because for end device signal is getting transmitted by output driver of level translator).

Thanks

Ash

  • Hello Ashu,

    I just wanted to let you know that I'm gathering together some info that should answer your questions.
  • Hi Ashu,

    For 1.: Please see http://www.sigcon.com/Pubs/news/2_20.htm Use series termination at each source side (SOC and end device). Note that Zo is the cable impedance plus the on resistance of the mux plus the on resistance of the level translator circuit (assuming FET not buffered level translator). If you are using a buffered level translator then I need to know all devices, physical distances, cables, input receiver impedances etc. and my answers for 2. and 3. will change.It is important physically where the cable, mux and level translator are located relative to the SOC and end device. Please explain. Also, I assume that one source is tri-state when the other is driving the line.

    For 2.: Always at the receiver (SOC and end device) if using FET type level translator.

    For 3: Same answer as for 2.

  • hi Jeff,

    Thanks for your info.

    I want to know what happen if my level translator is buffer instead of FET.
    What will happen with all my three problems ?

    Thanks
    Ash
  • 1. Place series termination at each source. In your case, the SOC, LT and end device can all be sources in a bidirectional system.
    2. Test Points at each receiver (LT, SOC and end device)
    3. Make measurements at each TP in 2.