PCA9306: Suitable for 1.8V <-> 3.3V, 2.5 MHz Ethernet MDIO/MDC usage?

Hello Jonathan,

To answer your question, yes, the PCA9306 is suitable for Ethernet MDIO applications and has been successfully implemented.

First, regarding the bandwidth, you are correct. The goal for reliable communication is to have greater than -3db of bandwidth at the 5th harmonic of the fundamental clock frequency. Figure 3 of the datasheet gives the bandwidth curve which shows there is >100Mhz of bandwidth at the -3db knee and will easily handle the 5th harmonic of 12.5Mhz for your 2.5Mhz MDC clock signal.

Regarding the pullup resistors, the datasheet leaves a little bit of room that could cause confusion between the following two statements that I will try to clarify.

In section 9.1.1 states " As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the translator bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor."

In section 9.2.2.1 states "The I2C bus master output can be push-pull or open-drain (pullup resistors may be required) and the I2C bus device output can be totem pole or open-drain (pullup resistors are required to pull the SCL2 and SDA2 ouputs to Vdpu). However, if either output is push-pull, data must be unidirectional or the outputs must be 3-state capable and be controlled by some direction-control mechanism to prevent high-to-low contentions in either direction. If both outputs are open-drain, no direction control is needed.

Since we are discussing the MDC Clock signal, I will use the SCL1/SCL2 pins in my description. But this is just a naming convention and there is no difference between the SCL and SDA pins from a physical perspective.

Visualize a FET between the SCL1 and SCL2 pins with the Source connected to SCL1, the Drain connected to SCL2 and the Gate connected to the EN pins. Also, from the datasheet, the EN and VREF2 (drain) are connected together to Vdpu.

For push-pull applications, the pullup resistor can be removed from the SCL1 side of the device as long as the data is unidirectional and flowing into the the SCL1 side of the device and out of the SCL2 side. When the MDC signal is pulled "low," SCL1 is essentially grounded and the Vgs of the FET becomes greater than the threshold establishing a channel between the Drain (SCL2) and the Source (SCL1). At this point current will start to flow pulling down the SCL2 side.

When the MDC signal is pushed "high," the Vgs becomes less than the threshold and the channel between SCL1 and SCL2 dissipates. SCL2 is then pulled high through the required pullup on SCL2.

It is important to note that even though the SCL1 pin is driven high and low, it is required to sink the current of all pullup resistance on the SCL2 side of the device when the signal is "low." The value of the pullup resistor should be chosen such that it does not exceed the MDC Source's current sink specification.

Finally, the last point of clarity I would like to make is that the SCL and SDA channels of the device are independent of each other. The statement that "if either output is push-pull, data must be unidirectional..." is on a per channel basis. This means that the MDC signal can be used in the Push-Pull configuration and the MDIO can be used in the open drain configuration with a pullup on both sides of the PCA9306 device without any problems.

I also don't recall a specific Rise/Fall time in the MDIO specification but I do believe the total bus capacitance is specified. I also know from personal experience that the total bus length is critical and needs to be short enough that reflections are not introduced. With some level auto-sensing bi-directional level shifters, reflections can cause the direction to switch which then corrupts the data that is still trying to be transmitted. But as long as you have a well-behaved bus, the PCA9306 should be a good device for your application.

I hope this detailed response answers all of your questions and concerns.

Regards,
Jonathan

Hi Jonathan,

1. Yes, I think if you scaled the clock speed to 10MHz you would be OK based upon the published information.  I haven't personally tried to run it that fast so I can't speak with 100% certainty.  But from the bandwidth curve, it should be feasible.  There will be other factors you would need to consider such as the total bus capacitance and loading along with the pullup resistor strength, etc. for your actual bus.  Some other parameters might dictate the maximum speed you could achieve so it might be worth a quick evaluation to be sure.

2. No, the LSF0102 and PCA9306 are very comparable devices and either one should work equally well in your application.  And regarding my comment about the reflections causing erroneous direction changes, either the PCA9306 or LSF0102 are probably less susceptible to problems than some of the other level shifters with different architectures.  For example, the TXS0108 devices uses edge rate accelerators (one shots) to improve the overall data rate.  .  These can be problematic with reflections.  However, the PCA9306 and LSF0102 have a simpler architecture and should recover quickly once the voltage crosses above the threshold value again.

Also, for clarification on my previous description of how the level shifting happens, there is no dedicated source or drain side of the FET.  The design is such that if either side is pulled below the threshold voltage the FET is disabled.  When the MDC data is push/pull, the data is uni-directional and it can be assumed the source side will be from the controller side.  However, when the data is bi-directional with pullups on both side, a voltage shift on either side of the device will cause the FET to respond as if that side was the "source" side.

Regards,

Jonathan