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DS90UB913A-Q1: PDB Ramp Up

Harish kumar
Intellectual 435 points

Part Number: DS90UB913A-Q1

Is there any requirement that PDB signal should not be enabled unless the Pixel Clock is not stable on DS90UB913A/14A?
If yes, then what will be the impact if the PDB is enabled before the PCLK?

  • 0
    TI__Intellectual 1500 points
    The PDB pin on the device must be ramped after the VDDIO and VDD_n supplies have reached their required operating voltage levels. It is recommended to assert PDB = HIGH with an RC filter network to help ensure proper sequencing of the PDB pin after settling of the power supplies. It is related to power supply requirement than the clocking. I do not see any co-relation between PCLK application and PDB.
  • 0 in reply to Ankur Verma
    Intellectual 435 points
    Thanks Ankur,

    What should be PDB ramp up delay for reliable operation, as this information is not available in datasheet.
  • 0 in reply to Harish kumar
    TI__Expert 3245 points
    Hi Harish,

    Please refer to section 9.1.2 of the datasheet for power up/ pdb sequencing and timing. If you're referring to a defined slew rate of PDB then we do not specify one. You can refer to figure 9 of the datasheet to see the relation to PCLK if you want to optimize the PDB turn on time to when the device can start sampling data. The important thing is to have stable VDDIO and VDDN supply lines prior to assertion of PDB.

    Regards,