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DS90UB953-Q1: MIPI and User rom data question

Part Number: DS90UB953-Q1
Dear All,
i have some questions regarding the  DS90UB953-Q1
1) A was looking at the 953 DS an my question is  : can we use the "User ROM data" ( page 51), and how  can we store our device ID to the "User ROM data"
2) the DS says that if 4 MIPI lanes is used the max speed per lane is 832Mbps , what is the max speed per lane if 1 or 2 MIPI lanes are used?
Best Regards.
  • The maximum rate is 832Mbps/lane (also in 1/2 MIPI lanes).  Also, the device ID in 0x00 can be used to assign any valid I2C ID. Please download the latest 953 datasheet from the sdsace/ internal sharepoint.  

  • Dear Ankur Verma,

    I'm looking at the  

    and it says :

    Supports 1,2 or 4 Lane

    – Supports up to 830 Mbps per lane (4 lanes)

    – Supports up to 1.5Gbps/lane (1 or 2 lanes)

    So if 1 or 2 MIPI Lanes are used there is 1.5Gbps/lane support ?

    How can I access the sdsace/ internal sharepoint?

    Best Regards.

  • Please contact your local TI sales representative who would have access to the internal sharepoint and can provide information post NDA.
  • Dear Ankur,

    we have TI NDA , and have the DS for DS90UB953. I asked the same questions our contact in TI and he pointed me to this forum.

    1)In preview DS from this link www.ti.com/.../ds90ub953-q1.pdf

    is says that if using 2 lanes the data rate per lane is 1.5Gbps.

    Is this correct?

    2)High Speed Data Out signals chapter of DS90UB953-Q1

    There is a statement if the link is running at the 4Gbps the AC capacitor should be 33nF, but if the device is running at lower data rates a larger coupling capacitor will be required.

    How can I calculate the capacitor for lower data rates? What is the connection between capacitor value and data rate?

    Best Regards.
  • Hi,

    1.) The data rate per lane can be up to 832 Mbps * 4 lanes = ~3.3Gbps. When you include header information like CRC, LV/FV, DC Balancing etc the effective video data bandwidth is reduced.

    2.) The simplest thing for you to do is look at the datasheet of the deserializer you intend to use and use that recommended AC coupling capacitance. This AC coupling cap is largely being determined by the backward channel rate that will exist on the line, you don't want to fully attenuate it and lose bcc communication. So for example if you intended to link to a 954 you can use the 33nF cap as suggested, but if you were going to a 964 then using a 0.1uF cap would probably be better.

    Regards,
  • Dear MIchael,

    1) I understand that when I use 4 MIPI lanes on 953 that the max video bandwidth is 800Mbps/per lane * 4 = 3.2Gbps.

    My question was if I use 1 MIPI lane on 953 is then the bandwidth in this one lane 1.5 Gbps as stated in this document www.ti.com/.../ds90ub953-q1.pdf ??

    So my system consists of a image sensor that has one MIPI lane with speed of 1.2Gbps and this is connected to 953, and on other side is 954. Then the data trough the coax will be 1.2Gbps , what is lower than the 3.2Gbps and in this case as stated in DS of 953 the AC cap should be bigger if the data rate is lower.

    2) Does the AC cap being determined by the BC rate and not the FC rate?

    Best Regards.
  • Yes, you can have a BW of 1.5Gbps.

    The caps are creating a high pass filter in conjunction with the cable impedance, 50ohms. Since the DOUTP line has 2 caps in series you'll need to halve that value and you can run a basic HPF calculation to determine your cut off frequency. You'll notice that all values discussed are more than capable of passing the Gbps range of FCC data, however you want to ensure that you're not attenuating the BCC data which is much slower. The 913 for examples has a BCC =~5.5Mhz whereas the 953/954 has a nominal BCC of 50Mhz.

    Regards,