Part Number: DS90CR287
Other Parts Discussed in Thread: DS90CR288A, , DS25BR400, DS25BR440
This is perhaps more of a question regarding CameraLink, but since it involves TI serializer/deserializer chips, thought I'd ask here. My question is how to setup clocking when using multiple DS90CR287/288 chips. If I were designing a CameraLink repeater, to support medium mode, up to 85MHz, and go longer distances, I'd use 2x DS90CR288A deserializers, and 2x DS90CR287 serializer chips. Let's say I want to put an FPGA in between the chips, to analyze the data, then pass it through. I'd clock the input registers using the '288 RxClkOut, constrain the inputs properly, and use an internal PLL for internal logic. I'd of course control the DS90CR287 PWR DOWN pins, based on the presence of a clock (or clocks) from the 288 chips. When redriving the data to the '287 chips, would it be best to drive them both with the same clock, to minimize inter-cable skew when running at 85MHz, and maximize operating cable distance on the TX side? And which clock would I use, one of the 288 clocks, or an internally generated clock? My initial thought is NOT to drive each 287 TxClkIn separately with each 288 RxClkOut, as there may already be some inter-cable clock skew present.
A minor secondary question, does the 288 need to have PWR DOWN controlled? I'd like to keep it powered up all the time, so I can monitor it's clock to see if something's been plugged in.
Thanks,
Paul
