This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TUSB9261: -

Part Number: TUSB9261


Hello everyone,

I am working on a project where the TUSB9261 chip is used to connect the USB3.0 port of an Intel processor to a SATA NAND memory.

The problem we are facing is that TUSB9261 is not enumerated by the Device Manager of the Windows OS that is running on the Intel processor.

After I installed TI Flash Burner (the installation was done without internet connection) , I did not see any component under My computer icon in the GUI window of the TI Flash Burner.

Our design for TUSB9261 chip is characterised by: 

  * 1V1 power line comes in the same time as 3V3 power line;

  *  the reset is released 2s after the power lines are stable;

  * there is a 40 MHz clock that is clocking TUSB9261 - both FREQSEL0 and FREQSEL1 pins are pulled up using a 4k7 ohm resistors 

  * there is an SPI memory attached to TUSB9261;

  * we are not using either JTAG or UART debug port;

  * we are not using  USB_DP or USB_DM lines;

 * there is no firmware flashed on the SPI memory;

  * the Intel processor is not using ICH9M IP Controller for the USB board;

After I failed several times to detect the chip using Windows OS, I wanted to see what is happining also under Linux.

After running dmesg command, I can see that there are several trials to connect to the high speed lines, but none of the them is completed.

The messages I received are : new full-speed USB device number 1 using xhci_hcd

                                                       ..............................................................................................

                                                      new full-speed USB device number 4 using xhci_hcd

                                                      new full-speed USB device number 5 using xhci_hcd

                                                      ..............................................................................................

                                                     new full-speed USB device number 7 using xhci_hcd

                                                     new full-speed USB device number 8 using xhci_hcd

but I have only one device that is using xhci_hcd line.

For both Windows and Linux OS I tried to detect the chip with and without the SATA NAND memory, but with no success.

1. Can you give me an advice on how to make TUSB9261 to be visible by the system ? 

2. Is the 3V3 power line sensitive to any noise before the 3V3 is fully up ? 

Thank you in advance,

Monica

  • Hello,
    Please provide your schematic for review.
    What do you mean by "...* we are not using USB_DP or USB_DM lines;..."
    The communication with the OS is through the USB interface.
    regards
  • Hello Elias,

    Here is our schematic for the USB3.0 to SATA bridge. 

    The OS is communicating with the bridge through USB3.0 connection.

    Thank you,

    Monica

  • Hello,
    The schematic looks correct.
    Is this a bus-powered application?
    You should be able to see an HID instance on the Device manager, do you?
    Can you generate a GRSTz after power-up?
    What is the state of GPIO7 ? I'm wondering if the Host is going to compliance because it fails to detect the SS terminations on the TUSB9261 because it is still in reset state.

    Regards
  • Hello,
    I will answer step by step to your questions.

    1. Is this a bus-powered application ?
    Answer: No, the application is not bus powered; 3V3 and 1V1 are generated separately.
    Our power sequence was initially like this: VBUS, 1V1, 3V3
    After your comment I put a switch that selects VBUS, so the present power sequence is 1V1, 3V3, VBUS
    The TUSB9261 is not enumerated by device manager.

    2. You should be able to see an HID instance on the Device manager, do you?
    Answer: I am not able to see the HID instance on the Device Manager.

    3. Can you generate a GRSTz after power-up?
    Answer: I generated a GRSTz after power up, which was less than 100ms, but I did not obtain an enumeration of the device.

    4. What is the state of GPIO7 ?
    Answer: GPIO7 is 200mV.

    My comments:
    1. For this chip, at power up, the sequence is as follows: 1V1, 3V3 and afterwards GRSTz is released
    2. my SPI FLASH memory is empty, so I don.t undersand why GPIO7 is important ?

    Regards,
    Monica
  • Hello Elias,

    I have tried another TUSB9261 chip and I looked at several signals:

    1) GPIO1 and GPIO5 waveforms at start-up.
    Both GPIO1 and GPIO5 have a pulse of 50ms when they are at 1V in the same time and afterwards they get to 0.

    2) GPIO7 is all the time zero

    3) SPI_SCLK has a pulse of around 50 ms at 3V3 and afterward it gets to 0.

    How shall I interprete all these signals ?

    As I mentioned also in my last post, the SPI memory that is attached to TUSB9261 is empty.

    Can you tell me what functions or purpose has the bootloader that is in the TUSB9261 ROM memory ?

    Table 1. GPIO/PWM LED Designations in tusb9261Datasheet.pdf document can be taken into account when there is no firmware in SPI_FLASH memory ?

    Regards,
    Monica
  • Hello,
    The bootloader will bring up a HID instance, this HID instance will be enumerated by the USB Host and it is used to download the firmware to the SPI using the flash burner tool, once the firmware is loaded into the TUSB9261's RAM , it will re-enumerate with a mass storage instance ready to connect the SATA drive.
    Table 1 is true only when the firmware is loaded.
    Regards
  • Hello Elias,

    Thank you for your support.
    The problem with the TUSB was solved.


    3V3 power line was coming after 1v1, but with e significant delay of aprox 7ms.
    After I changed the delay to 1ms I was able to see the enumeration of the TUSB bootloader in Device Manager list.

    Still the visibility of the device was constrained by the disconnection and reconnection of the VBUS line.

    Regards,
    Monica