DS110DF111: Various Questions

Question 1 - For the 0.022uF capacitor in series between LPF_CP_A/B and LPF_REF_A/B, the evaluation board documentation shows a 0.022uF 0201 size X5R 15% capacitor. Would an NPO or X7R temperature coefficient improve the performance for -40 to +85 Celsius operating temperature?

Answer 1 - No the performance would be the same.

Question 2 - Would 5% or 10% capacitance tolerances improve the performance for an -40 to +85 Celsius operating temperature?

Answer 2 - A tighter capacitance tolerance would have some small benefit, but is not needed to meet datasheet specifications.

Question 3 - For the 25MHz oscillator, the technical data sheet recommend a standard 25MHz +/- 100ppm oscillator. The evaluation board documentation shows a +/- 50ppm oscillator with a 15pF output load capacitance.

Answer 3 - Any oscillator with 100 ppm or less will allow the DS110DF111 to operate and meet datasheet specifications.

Question 4 - Would there be any CDR performance improvement or degradation if using a +/- 50ppm or +/- 100ppm oscillator?

Answer 4 - No improvement.  The reference clock is only used to ensure locking at the precise datarate.  The oscillator input is not needed after the CDR has acquired lock.

Question 5 - Specification 6.3 Recommended Operating Conditions (Page 5) – This section states that the SMBus (SDA, SCL) recommended operating conditions as 3.0V to 3.6V. The electrical characteristics of the SDA/SCL indicate operations between 2.1 and 3.6V.  If the DS110DF111 is operating in 2.5V mode, would there be issues if the SMBus (SDA, SCL) interface is operating at 2.5V operation?  We understand that the SDA, SCL communications are OD.

Answer 5 - The SDA and SCL pins are 3.6V tolerant at all times.

Question 6 - Specification 6.5 Electrical Characteristics (Page 7) Propagation Delay (TPD) – Assuming the CDR is locked to the input signal, can you specify what parameters (input signal characteristics and register settings) which will produce the maximum propagation delay?

Answer 6 - The propagation delay is consistent across register settings and input signal characteristics.  The propagation delay is approximately 1.5UI + 200ps.  For a 10 Gbps datarate the equation is 150ps + 200ps = 350ps

Question 7 - Specification 6.5 Electrical Characteristics (Page 7) CDR Lock Time (TLOCK1) shows 10-30ms per DS110DF111 settings, data rate, and input channel. Assuming an optimal signal or field of merit, can you specify what input signal characteristics and register setting which will produce the maximum CDR lock time.  For example, which will take longer

Answer 7 - The primary components to lock time are input signal strength and the Rate/Subrate setting.  A weak signal will force the DF111 input to take more time to adapt at each Rate/Subrate setting given in the table.  When multiple divide ratios and VCO ranges are available the lowest rates are checked first, so the higher rates will have a longer lock time.

Question 7a - CTLE adapt until lock or optimum with or without the DFE. In addition, CTLE requires direct register lookup due to divide by 4/8 setting.

Answer 7a - By default the CTLE will use a single setting in the /4 and /8 VCO ranges.  The CTLE value is given in register 0x3A.  We recommend to use a lower CTLE setting for this condition, by default register 0x3A = A5'h, change this value to 0x3A = 00'h.

Question 8 - Figure of Merit Type Settings (Table 22). Can you provide general guidelines on FOM settings for different types of transmission media?

Answer 8 - The default Figure of Merit setting works best in 99.9% of applications.  I would not change this value.

Question 9 - Please confirm for register 0x2C 0x0 and 0x3 set both HEO and VEO simultaneously.

Answer 9 -  The only valid combination in register 0x2C to set HEO and VEO simultaneously is the default setting of  0x2C[5:4] = 11'b

Question 10 - CTLE Settings for Adaption, Register 0x40-0x4F (Table 23). Can you please provide the characteristics of CTLE Boost String shown in Table 23 with respect to signal levels or loss and frequencies?

Answer 10 - The CTLE table gives a range of CTLE values with gain values of 3 - 25 dB at 6 GHz.  The lowest setting at 0x40 is ~ 3-4 dB gain and the highest setting at 0x4F is over 25 dB of gain.

Question 11 - Table 18 EOM voltage range in peak-to-peak voltage does not correlate equally in magnitude to Table 26 RMS voltage levels. Is there a reason?

Answer 11 -  The Table 18 EOM range is the total range.  The Table 26 values show the voltage grainularity.

Question 12 - Are there any application guidelines on the EOM settings in register 0x11 [7:6] to compute a FOM for automatic adaptation of the CTLE and the DFE?

Answer 12 - The EOM settings are only a scaling factor to better see the eye opening.  They do not impact the adaption algorithm for the CTLE or DFE.

Question 13 – The DS110DF111 cannot retime the following bit rates

a) 614.4 Mb/s

b) 768 Mb/s

Answer 13 - These bit rates fall outside the normal range.  To pass this data with the DS110DF111 I would recommend using "Raw" data mode and bypassing the CDR.  In this configuration the DS110DF111 will act as a repeater with a CTLE front end.