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Linux/DP83822HF: DP83822HF FX Not working.

Part Number: DP83822HF
Other Parts Discussed in Thread: DP83822IF

Tool/software: Linux

Hi.

I'm using AM572x custom board

and, DP 83822HF is connected to RPU2 ETH0/ETH1

I have question.

Q1. GENCFG(0x465) "phy_read" value is invalid.

        The value does not changed when i set  "phy_write(phydev, 0x465, 0x1);"

==== DP83822HF_read_status 761===
BMCR(0x0): 0x3100
BMSR(0x1): 0x7849
PHYIDR1(0x2): 0x2000
PHYIDR2(0x3): 0xa240
CR1(0x9): 0x0
CR2(0xa): 0x4100
PHYSCR(0x11): 0x4100
RCSR(0x17): 0x41
LEDCR(0x18): 0x400
PHYCR(0x19): 0x21
GENCFG(0x465): 0xffffffea
=================

Q2. DP83822HF Reg value is correct.
       But, I don't know why FX not working.

Best Regards

John

  • Hi John,

    The register in question, 0x465, is an extended register and as such has a different access method than the other registers in your status dump.

    I am not sure how the AM572x MDIO access is created, but you will likely have to use the indirect access method described in section "8.4.2.5 Read (No Post Increment) Operation" of the DP83822HF datasheet.

    I am not sure what your question is in Q2. Can you elaborate?

    Best Regards,
  • Hi,

    Thank you for your reply.

    I need to operate DP83822HF in FX mode.


    Q2. I wrote 0x4000 to the CR register, but it didn't work.
    Are there any other settings besides FX_EN?


    Best Regard,
    John
  • Hi John,

    You should only have to set bit[14] of the register address 0xA to get FX mode enabled. You said you write 0x4000, but there is a reserved field that should NOT be modified.

    Please read the default value of 0xA register, then set bit[14] and do not change any of the other bits.

    Could you also provide a schematic of only your PHY?

    Best Regards,
  • Hi Rodrigues,

    I am already set bit[14] and do not change any of the other bits.

     

    CR2 Reg val is 0x4100.

    Are there any other settings besides FX_EN?

    ------------------------------ reg set code ------------------------------------------------

    val = phy_read(phydev, 0xA);

    val |= 0x4000;

    phy_write(phydev, 0xA, val);

    -------------------------------------------------------------------------------------------------

    Schematic file.

    PRU2_1_FX.PDF

    ==== DP83822HF_read_status 761===

    BMCR(0x0): 0x3100

    BMSR(0x1): 0x7849

    PHYIDR1(0x2): 0x2000

    PHYIDR2(0x3): 0xa240

    CR1(0x9): 0x0

    CR2(0xa): 0x4100

    PHYSCR(0x11): 0x4100

    RCSR(0x17): 0x41

    LEDCR(0x18): 0x400

    PHYCR(0x19): 0x21

    GENCFG(0x465): 0xffffffea

    =================

    Best Regard,

    John

  • Hi John,

    It looks like you are setting register 0xA properly but I do have 1 concern. Your schematic shows a bead and a 10nF cap only for the PHY. Please implement the cap decades required by the DP83822 datasheet.

    It may be possible that as you switch from TX to FX mode, the PHY is starving for current and causing a failue.

    Can you also strap the PHY into FX mode rather than change the register? You could also remove the bead from your design and replace it with a 0ohm resistor.

    Best Regards,
  • Hi Rodrigues,

    I tried both(FX Boot strap / DP83822 Datasheet guide).

    but, FX Mode is not working.

    I have question.

    how to configuration 'PECL termination resistance' of DP83822HF

     

    Best Regards,

    John

  • Hi John,

    The DP83822IF and DP83822HF are both current mode line drivers.
    They are not PECL and thus have different biasing.
    From your attached schematic it looks like you are not properly biasing the PHY.
    Please refer to page 89 in the datasheet (section 9.2.2) for information regarding proper fiber connection.

    You need to have 50 ohm terminations on TD and RD pins with a 0.1uF DC blocking cap.

    Kind regards,
    Ross
  • Hi Ross,

    I tried both(50 ohm / 0.1uF cap).
    but, FX Mode is not working.

    When trying to read register 0x0001 Basic Mode Status Register through MDIO the result is 0x7849 which denotes that the link and auto-negotiation bits are off. The LEDs show that the link and auto-negotiation have been completed.

    There is a similar case.
    URL: e2e.ti.com/.../2032488

    But I don't know why read 0x01 register requires two reads.
    Is this a connection to this problem?

    Best Regards,
    John
  • Hi John,

    BMSR requires 2 reads because the link bit is latched low for debug purposes. You must always read BMSR twice to see the link status.

    Best Regards,
  • Hi Rodrigues,

    I tried 2 reads. (BMSR:0x7849)
    but FX not working.

    Is there any other solution?
    Please advise me.

    Best Regards,
    John
  • I don't know SFP module signal.
    and
    i want to know wave signal about SFP module between phy(TD+, TD- , RD+, RD-).

    Best Regards
    John
  • Hi John,

    One of your problems may be your SFP has a LOS signal. In the diagram you posted earlier in the thread, the SFP shows a LOS or loss of signal pin. The DP83822HF supports a SD pin or signal detect.

    The LOS output from your SFP must be inverted to provide the proper SD input to the DP83822HF to indicate a link is available across fiber. You can do this by changing bit[0] in register 0x465 to 1.

    Also, which mode are you strapping the RX_ER pin to?

    Best Regards,
  • Hi Rodrigues,

    The LOS output from your SFP must be inverted to provide the proper SD input to the DP83822HF to indicate a link is available across fiber
    -> I already doing it.

    You can do this by changing bit[0] in register 0x465 to 1.
    -> I tried both. (changed bit[0] in register 0x465 to 1 or 0.)
    -> But, FX not working

    Also, which mode are you strapping the RX_ER pin to?
    -> I used RX_ER pin mode 1. It is RGMII_EN '0' and SD_DIS '0'.


    Best Regards,
    John
  • Hi Rodrigues,

    I have question.

    DP83822HF is not PECL.
    However, most SFP modules are PECL type.

    What type of module should I use?

    Best Regards,
    John
  • Hi John,

    It does not matter that the 822 is a current mode line driver and that most SFPs are PECL.
    This is why you have DC blocking capacitors. Please see the example diagram in the DP83822HF datasheet.
    You will see that we recommend 0.1uF DC blocking caps.

    Kind regards,
    Ross
  • Thnak you for your reply.

    I solved the problem.

    The problem was that phy addr were '0' both.. (PRU2-0 ADDR:0 / PRU2-1 ADDR:0)

    It was my mistake.

    Best Regards,
    John Kim