P82B96: About Low-level output voltage(VOL)

Hello Kanemaru-san,

This device, like many other I2C buffers, introduces a static voltage offset onto the low level of the "S" side as a mechanism for direction control. This helps in separating the transmit and receive paths, since otherwise a low level on the R input would always couple through on the T output (as if it were driven on S by another device). To avoid this coupling and allow for the directionality of the signals to be preserved, the device drives a VOL on the R output that is greater than its VIT (input voltage threshold).

Best regards,
Max

Kanemaru-san,

Yes, it looks like you understand it properly. If the S-side VOL were 0 V, then it would cause a low level to propagate onto the R output as well. You would not want this to occur when the R input is driven low.

Here is a summary of the behavior to hopefully make things more clear:
- If the I2C master drives the line low, the input voltage on S would be below its VIT spec. This means that the corresponding T output would go low.
- If the "other device" in your image drives the R input low, then the S pin would be driven to its VOL level. This is above its VIT spec, though, and so the corresponding T output would not go low.

Please let me know if this does not make sense.

Regards,
Max

Kanemaru-san,

Yes, your understanding is correct.

Regards,
Max

Hi Max-san,

Thank you for your prompt reply.

I understand. Thank you very much.

Regards,

Kanemaru