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DS90UB926Q-Q1: How to achieve FPD-LINK to RGB to FPD-LINK ,Through DS90UB926+DS90UB925 , please review the sch if can achieve , thanks

Part Number: DS90UB926Q-Q1

DS90UB 925926.pdf

I Want use the US90UB926+US90UB925 Achieve the FPD-LINK to RGB ,cure the RGB sihnal ,the convert PFD-LINK ,output to the display , but i have try many times , can not link ok ,please help review the sch in the attachment ,if the sch can achieve the FPD-LIN ---> RGB --->FPD-LINK , many thinks !

  • Andrew,
    1. please follow up the d/s design request. we can check the sch., but it seems NOT be clear, such as connector? does it follow up TI's recommendation? also, the UB925's PDB, why you have one pull-up and one pull-down resistor? TI recommends to use RC circuit for PDB..., so please check the control signals (PDB, INTB, MODE_SEL, etc...) are correct or not in your application based on d/s descriptions
    2. please debug the link step by step, you can use:
    a. I2C operation is well or not? if not, checking the I2C ID and SCL/SDA pull-up resistors, then check the power supplies are right or not?
    b. lock pin is high or not?
    c. data pattern can work well? (please check the app. note part number shown in d/s as well)
    d. bist test?
    in one word, please nail down the issue into chip level, NOT total system failure (such as: no display...).

    best regards,
    Steven
  • Dear Steven,

    thank you for your help !Kadjar_925B_926Q(V20) _ KADJAR_.pdf

    we  test the PCB of  ds90ub926+FPGA+ds90ub925. The DS90ub926 seems  could receive the FPD-LINK of the soerce (DS90UB925 in side),although the lock not steady .    the IIC/ HS/VS/DE/PCLK are link from 926 to 925 directly ,only the RGB througn the FPGA , the 926 IIC /PCLK  waveform seems normal ,  the925/926  Mode_sel all  select the firth one mode , but the 925 can not send the effective signal , the accessroy is the sch ,  would  you kindly give some advice ,many thanks !

  • Andrew, if you connect the HS/VS/PCLK from UB926 output to UB925's inputs, while RGB data is sent to FPGA, you should care for the timing requirements between data input and PCLK. This would damage your system. These timing requests are listed in d/s page13.

    best regards,

    Steven