DS90CF384: LVDS to Parallel Output Mapping for VESA 24 bit compatibility

I am planning to use a DS90CF384MTD IC in a design.

I have an Industrial temperature application receiving 24 bit LVDS Video from a SBC with a NXP PTN34601 LVDS bridge chip.

This chip can output 24 bit video in a VESA format output.

There is an example of the format in the NXP data sheet available online. It is shown as the following format:

NXP PTN34601 VESA Data Packing Format:
Channel | Bit Position
          6    5   4   3   2   1   0
A         G0   R5  R4  R3  R2  R1  R0
B         B1   B0  G5  G4  G3  G2  G1
C         DE   VS  HS  B5  B4  B3  B2
D         na   B7  B6  G7  G6  R7  R6

Do I need to translate these bit positions into the decode table shown on page 10 of the DS90CF384 data sheet.

Do you have an design example of the color bit assignments to decode this data format for a parallel TTL input LCD display we will be using?

Thank you for any assistance.

James Fults, Terry Harikul

IEE Inc

Van Nuys, Ca.