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TLK10031: Reference Clock Design

Yaoting Yang
Intellectual 780 points
Part Number: TLK10031
Other Parts Discussed in Thread: CDCM7005, TLK10002, CDCM6208

Hi,

We are designing a 10Gbase optical fiber Ethernet phy link by using TLK10031 at one end, and at the other end a general 10Gbase Ethernet pcie card is expected to be hooked up.

My issue is how to design a reference clock for tlk10031.

TLK10031 has a CLKOUT port, one approach is to connect this port to a jitter cleaner like CDCM7005, which generates a clock as to be TLK10031's reference clock. Another approach is to use a crystal oscillator that generates a reference clock independently for TLK10031. My question is, which one is TI's preferable chose? Is there any clock synchronization requirement for TLK10031 with other end's pcie card?

Is there anyone who can help?

Appreciate a lot!

  • 0
    TI__Genius 16150 points

    Hi Yaoting,

    TI recommends using a clock synthetizer IC along with the crystal or crystal oscillator to provide a low-jitter differential clock signal to the REFCLK inputs. Examples, would include CDCM6208 or one of the LMK series from SVA. Here is an applications note that talks about the combined performance of CDCM6208 with the TLK10002:

    Best Regards,

    Luis Omar Moran

    High Speed Interface

    SWAT Team

  • 0 in reply to Luis Omar Moran
    Intellectual 780 points
    Thank you, Luis.
    Sorry, I have not expressed my question clearly. My question is, for the CDCM7005 (we have it by hand) its REF input, we have two choice : either by using the clock from an independent XO locally or by using the CLKOUT clock signal from TLK10031. It depends on whether TLK10031 has the clock synchronization requirement with an external counter part transceiver's clock, I think. I have no idea of which will be preferred by TI, CLKOUT signal or any proper local signal to the CDCM7005's REF pin. Looking forward to helps!
  • 0 in reply to Yaoting Yang
    TI__Genius 16150 points
    Yaoting,

    I suggest the CLKOUT signal, even you could take a look into Figure 10-5 of datasheet that shows an external clock jitter cleaner connection.

    I hope this helps.

    Thanks,
    Luis
  • 0 in reply to Luis Omar Moran
    Intellectual 780 points
    OK, thanks.
    A related question is, the line's byte frequency should be 10.3125G/20 in 10GKR mode, am i right? On spec page 72, in table 7-36, is the divider value (bit7~bit4) based on this byte frequency?