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TSB81BA3E: Looking for 3 port HUB reference design, WITHOUT a LLC

Glenn Stern
Prodigy 10 points
Part Number: TSB81BA3E


I saw the other discussion from 2013 about the "D" chip, but no answer was really provided there since there are no schematics available I can find for the "OHCI" board people were talking about.  But the point is, most good datasheets show a basic "get it working" schematic with needed caps/resistors/osc's, and detail on most pins.  The DS for this part is really stripped as far as reference schematics go...sure it has some interface stuff on the small # of FW bus pins, but big deal, I could find those references in many places.  What's most important is the detail on the remaining 70 or so pins.  As my title says, I ideally want to make a dumb hub, and I understand the ports repeat data when no LLC is running, but there is no clear/concise explanation of how to strap ALL the unused pins to fool the part to work in echo mode with no LLC (I see lots of talk about power down states, which I assume I can't tolerate.  Any help would be great gang.

  • 0
    Guru 317480 points

    The PHY/LLC interface is specified in chapter 17 of IEEE1394-2008.

    Anyway, page 16 of the datasheet says:

    The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB81BA3E detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB81BA3E continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface.

    So the most important thing is to keep LPS low. As for the other LLC interface pins: CNA, PINT, and PCLK are outputs, so they can be left open. The bidirectional CTL0/1, D0…7 signals and the LCLK/LREQ inputs have bus holders, so they can be left open.

    All the other input pins are explained in the datasheet.

    For the actual ports, see the datasheet, and any 'normal' example schematic.