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HD3SS3220: Timing Requirements I2C clock

Guenter Uhlrich
Prodigy 10 points
Part Number: HD3SS3220

Hi,

the maximum allowed I2C clock frequency is unclear to me.

Based on HD3SS3220 datasheet from "SLLSES1C –DECEMBER 2015–REVISED MAY 2017" section "6.6 Timing Requirements" table entry "fSCL" the SCL clock frequency is given as maximal  "100 ns". Which means to me a minimum of 10Mhz is required, I know this is bullshit.

So what is the maximum SCL clock frequency. 100kHz, 400kHz or even better?

  • 0
    TI__Intellectual 1165 points
    Hi,

    please use 400kHz as maximum SCL clock frequency.

    Best regards
    Cevin
  • 0 in reply to Cevin
    TI__Intellectual 2650 points

    Hello Cevin,
       My costomer has same question about fSCL on HD3SS3220.

    I think HD3SS3220 I2C Engine looks like suported STANDARD-MODE(~100KHz).
    Because of;
    The following is the quatation of HD3SS3220 I2C timing spec vs I2C F/S-mode spec.
    ---- Quotation from HD3SS3220 DataSheets
     
    ---- Quotation from NXP(Philipps) I2C spec
     　
    As of HD3SS3220 timing spec, it may not support "400kHz as maximum SCL clock frequency"
    Could you comment about this inconsistency?


    Thank you in advance,
    Matsuro Koterasawa/TIj CSC

  • 0 in reply to m.k
    TI__Intellectual 2650 points

    Hello HD3SS3220 team,

       Is there any update?

    If DataSheet is just typo of  "fCLK  100ns_max" instead of  "fCLK   100KHz_max",
    then We will use 100KHz.
    If it supports 400KHzFAST-MODE, I would like you put the discription on D/S.

    Please advice me to confirm.

    Thanks,
    matsuro

  • 0 in reply to m.k
    TI__Intellectual 1165 points
    Hi,

    please excuse the delay, HD3SS3220 supports 400kHz I2C with all respective timings and the datasheet will be updated to reflect this.

    Best regards
    Cevin