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SN65DSI85-Q1: Dual DSI to Dual LVDS Register Setting issue

khemraj suthar
Prodigy 170 points
Part Number: SN65DSI85-Q1
Other Parts Discussed in Thread: SN65DSI85

Hi All,

We are using an LVDS display in our product and we wanted to interface the LVDS display with qualcomm snapdragon 820 processor which support MIPI display. To convert MIPI to LVDS we have used SN65DSI85 in our design.

Our use case is transmitting Dual Split DSI output from processor i.e. half image of the complete display will be transferred to One DSI 4 lane port and other half display will be transferred to second DSI 4-lane port. We want the same scenario on the LVDS side that one display on LVDS1 will show the half portion of the complete image and second display will show the remaining half portion of the complete image.

I have attached the register settings with the case and below are our observations:

1.) We are able to receive the DSI data and clock lanes on the input side of SN65DSI85 both DSI ports.

2.) We are not able to receive the LVDS signals on both the LVDS ports. Only one port is working at a time. We want to see both the LVDS port working at the same time.

3.) The resolution of the display is 720P@60fps.

4.) The data on LVDS single port also sometimes doesn't work and sometimes it work.

Can somebody please verify the register setting  and let us know the exact settings we need to use.

Setting of SN65DSI85.doc

  • 0
    TI__Mastermind 18655 points
    Hi Khemraj,

    Please, double check that you are following the initialization sequence requirement as shown in the Figure 4. "RESET and Initialization Timing Definition While VCC is High".
    It is required by the MIPI spec for the host to drive all the DSI outputs to LP11 prior to the transition to HS mode.

    We also need to you to check the IRQ registers at offset 0XE5 and 0XE6.

    Please, share the panel datasheet we need to check the video timing parameters.

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 170 points

    Hi Joel,

    Thanks for the inputs. We will verify the initialization sequence and IRQ registers value. Meanwhile please see the below information which we have in the panel datasheet:

    LVDS Panel Information : 


    Features : 

    Pixel Clock Frequency : 25MHz (Min) - 75MHz (Max)

    Please verify the sequence of the LVDS display with the register settings shared in previous email.

    DSI Information : 

    MIPI CSI Differential Clock  : 180Mhz

    Two MIPI 4-lane and 1 Clock lane ports

    Resolution : 1280 x 720 @60fps 

    Your response will be highly appreciated.

  • 0 in reply to khemraj suthar
    Prodigy 170 points

    Hi Joel,

    We have checked the status of the IRQ register and below is the information :

    When video out on single LVDS 1 - 0xe5 = 0x35, 0xe6 = 0x2c

    When no video out on single LVDS - 0xe5 = 0xb5, 0xe6 = 0x3c

    In both the case LVDS CHB is not working.

    Please review the complete section and let me know the resolution for this issue.

    Regards,

    Khemraj

  • 0 in reply to khemraj suthar
    TI__Mastermind 18655 points
    Hi khemraj,

    Confirm if the LVDS clock output is running at the correct frequency, levels, no jitter.

    Use the formula bellow to calculate the minimum DSI Clock frequency based on the your panel settings.

    Stream Bit Rate = PixelClock × bpp
    Stream Bit Rate = 69 x 24 = 1.656 Gbps
    Min Required DSI Clock Frequency = StreamBitRate / (Min_Number_DSI_Lanes × 2)
    Min Required DSI Clock Frequency = 1656 / ( 4 x 2 )
    Min Required DSI Clock Frequency = 207 MHz

    The CHA_DSI_CLK_RANGE and the CHB_DSI_CLK_RANGE field are incorrect.

    Lets suppose we want to configure a DSI Clk of 207 MHz, the CHA_DSI_CLK_RANGE should be 0x29.

    Confirm that the panel supports our FORMAT 1 at 24pp.

    Please, try the internal pattern mode.

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 170 points

    Fullscreen sn65dsi85_testpattern.txt Download 
    i2cset -y 3 0x2c 0x09 0x00
i2cset -y 3 0x2c 0x0A 0x03
i2cset -y 3 0x2c 0x0B 0x10
i2cset -y 3 0x2c 0x0D 0x00
i2cset -y 3 0x2c 0x10 0x20
i2cset -y 3 0x2c 0x11 0x00
i2cset -y 3 0x2c 0x12 0x24
i2cset -y 3 0x2c 0x13 0x00
i2cset -y 3 0x2c 0x18 0x00
i2cset -y 3 0x2c 0x19 0x00
i2cset -y 3 0x2c 0x1A 0x03
i2cset -y 3 0x2c 0x1B 0x00
i2cset -y 3 0x2c 0x20 0x00
i2cset -y 3 0x2c 0x21 0x05
i2cset -y 3 0x2c 0x22 0x00
i2cset -y 3 0x2c 0x23 0x00
i2cset -y 3 0x2c 0x24 0x00
i2cset -y 3 0x2c 0x25 0x00
i2cset -y 3 0x2c 0x26 0x00
i2cset -y 3 0x2c 0x27 0x00
i2cset -y 3 0x2c 0x28 0x21
i2cset -y 3 0x2c 0x29 0x00
i2cset -y 3 0x2c 0x2A 0x00
i2cset -y 3 0x2c 0x2B 0x00
i2cset -y 3 0x2c 0x2C 0x24
i2cset -y 3 0x2c 0x2D 0x00
i2cset -y 3 0x2c 0x2E 0x00
i2cset -y 3 0x2c 0x2F 0x00
i2cset -y 3 0x2c 0x30 0x03
i2cset -y 3 0x2c 0x31 0x00
i2cset -y 3 0x2c 0x32 0x00
i2cset -y 3 0x2c 0x33 0x00
i2cset -y 3 0x2c 0x34 0x20
i2cset -y 3 0x2c 0x35 0x00
i2cset -y 3 0x2c 0x36 0x00
i2cset -y 3 0x2c 0x37 0x00
i2cset -y 3 0x2c 0x38 0x00
i2cset -y 3 0x2c 0x39 0x00
i2cset -y 3 0x2c 0x3A 0x00
i2cset -y 3 0x2c 0x3B 0x00
i2cset -y 3 0x2c 0x3C 0x00
i2cset -y 3 0x2c 0x3D 0x00
i2cset -y 3 0x2c 0x3E 0x00
i2cset -y 3 0x2c 0x0D 0x01

#1280
i2cset -y 3 0x2c 0x20 0x00
i2cset -y 3 0x2c 0x21 0x05

#1280
i2cset -y 3 0x2c 0x22 0x00
i2cset -y 3 0x2c 0x23 0x05

#720
i2cset -y 3 0x2c 0x24 0xD0
i2cset -y 3 0x2c 0x25 0x02

#720
i2cset -y 3 0x2c 0x26 0xD0
i2cset -y 3 0x2c 0x27 0x02

#Enable test pattern
i2cset -y 3 0x2c 0x3c 0x11

    Hello Joel,

    Thanks for your update. Yes, the panel supports Format1 @24bpp.

    Below are our observations.

    #1. With attached test pattern register settings, we are getting LVDS out on both the channels and verified the pattern on display.

    #2. With DSI to LVDS configurations as attached earlier, no output on LVDS_CH_B. We have verified the signals, and there is output on both the DSI channel(DSI0 & DSI1) on host side. On LVDS side, we are getting output on LVDS_CH_A (display attached and it is showing the content), but no output on LVDS_CH_B, we are getting clock on pins 53,54 (B_CLKP, B_CLKN) but no activity on data lines of LVDS_CH_B. Is there anything we are missing for LVDS out for both the LVDS?

    Thanks.

  • 0 in reply to khemraj suthar
    TI__Mastermind 18655 points

    Hi Khemraj,

    Please, try the attached device configuration that I generated based on the panel spec. You can use the DSI Tuner to load the .dsi  file and check the how each field was configured. Let me know if you have any question or comments on it.  I would suggest trying the attached test pattern first.

    DSI85_Dual_to_Dual.zip

    I will be very helpful if I can get full access to the panel spec. You can send it via email to joel.jimenez@ti.com

    Regards