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SN65DSI86: SN65DSI86 losing lock

Dan Andersen
Genius 11460 points

Part Number: SN65DSI86

My customer is seeing display failures on a product using the SN65DSI86.  When it fails the PLL os the DSI86 is not locked (based on register 0x0A) and the main link id is off (reg 0x96).  On their board VCCIO trails VCCA by 250ms.  The datasheet does not appear to specify a maximum time for VCCA to be stable before VCCIO.  Would this delay be reason for the failures?  They are seeing this on about 50% of units.  Any other thoughts on cause?  We will be visiting the customer lab tomorrow for a deeper look.  If there is anything else we should look at please let us know.

Thanks,

Dan

  • 0
    TI__Mastermind 18655 points
    Hello Dan,

    I will confirm if there is a maximum time requirement.

    Please, provide the provide and confirm the following:
    Clock source. Reference clock or DSI CLK. Programmed frequency and actual input clock frequency.
    Are the DSI lanes in LP11 state before EN assertion?
    Is REFCLK active and stable before EN assertion?
    Are VCC/A and VCCIO/VPLL stable before EN assertion?

    Regards
  • 0 in reply to Joel Jimenez0
    TI__Genius 11460 points

    • Clock source. Reference clock or DSI CLK. Programmed frequency and actual input clock frequency.  From our discussion yesterday this appeared to be a 27MHz external crystal.  I expect the programmed frequency to show up in the register settings.

      • Clock source is a 27MHz oscillator. Programmed frequency shows up when display is good. When display do not work 19.2MHz shows up in register.

    • Are the DSI lanes in LP11 state before EN assertion?

      • Looking at the code looks like DSI lanes goes to LP11 after EN assertion. We are further investigating this.

    • Is REFCLK active and stable before EN assertion?

      • Yes.

    • Are VCC/A and VCCIO/VPLL stable before EN assertion?

      • Yes

    • I can send the schematic of SN65DSI86 circuit and REFCLK directly for your review if desired. 

    • Scope shot of VCC, VCCIO/VPLL, EN, and REFCLK for “good” and “bad”:

      GOOD:

      • BAD:

    • Register sets for “good” and “bad”

    • BAD

      No size specified (using byte-data access)
           0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
      00: 36 38 49 53 44 20 20 20 02 00 0c 00 00 00 00 00    68ISD   ?.?.....
      10: 3e 00 41 00 00 00 00 00 00 00 00 00 00 00 00 00    >.A.............
      20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
      30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
      40: 01 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00    ?...?...........
      50: 00 00 00 00 00 00 20 00 40 e4 05 00 10 00 e0 00    ...... .@??.?.?.
      60: a0 60 a4 00 00 00 00 00 00 00 00 00 00 00 00 00    ?`?.............
      70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
      80: 00 00 00 00 00 00 00 00 00 1f 7c f0 c1 07 1f 7c    .........?|????|
      90: f0 c1 07 04 00 00 0a 04 01 00 00 00 00 00 00 00    ????..???.......
      a0: 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............
      b0: 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c    ?x???l???\\\????
      c0: 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00    ???.............
      d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
      e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
      f0: c0 03 00 00 00 02 00 00 00 00 00 00 00 00 00 00


      Good

      No size specified (using byte-data access)
           0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
      00: 36 38 49 53 44 20 20 20 02 00 86 00 00 01 00 00    68ISD   ?.?..?..
      10: 26 00 5b 00 00 00 00 00 00 00 00 00 00 00 00 00    &.[.............
      20: 80 07 00 00 38 04 00 00 00 00 00 00 20 00 00 00    ??..8?...... ...
      30: 04 80 00 00 fc 00 2c 00 30 00 04 00 00 00 00 00    ??..?.,.0.?.....
      40: 84 48 00 00 80 00 cc 08 6c 04 1c 01 30 00 20 00    ?H..?.??l???0. .
      50: 04 80 80 07 38 04 00 00 40 e4 0d 01 11 00 e0 00    ????8?..@????.?.
      60: a0 60 a4 00 00 00 00 00 00 00 00 00 00 00 00 00    ?`?.............
      70: 00 00 00 00 00 01 02 01 80 81 00 00 00 00 00 00    .....?????......
      80: 00 00 00 00 00 00 00 00 00 1f 7c f0 c1 07 1f 7c    .........?|????|
      90: f0 c1 07 24 80 00 01 04 01 00 00 00 00 00 00 00    ???$?.???.......
      a0: 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............
      b0: 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c    ?x???l???\\\????
      c0: 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00    ???.............
      d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
      e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
      f0: 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00    ....?...?.......

    Thanks,

    Dan

  • 0 in reply to Dan Andersen
    TI__Mastermind 18655 points
    Hi Dan,

    Please, send their schematics via email.

    It seems that the bad units the internal CSRs and functions are reset to default. It can be caused by the deassertion (low) of EN or VCC/A and VCCIO/VPLL are not stable.

    Are they are seeing this failure all the time in the failing devices?
    Can you swap the device to see if the failure follows the unit or the board?

    Regards,
    Joel
  • 0 in reply to Joel Jimenez0
    TI__Genius 11460 points
    Hi Joel,
    I will send their schematic over directly. The failure happens on any board, and will happen approximately 1 in 5 times that they boot up.
    Regards,
    Dan
  • 0 in reply to Dan Andersen
    TI__Mastermind 18655 points
    I have reviewed their schematics and got some comments:

    1. EN terminal does not need pull-up resistor.
    2. Do they have pull-ups in the I2C bus?

    We need to figure out why the registers are reset in the failing test. Please, monitor the EN terminal to confirm that it is asserted high for at least 1ms before starting the initialization of all CSR registers to their appropriate values.

    Regards