SN65LV1023A: Clarifying TX and RX clock spec

Aaron Jones

Part Number: SN65LV1023A

Hi TI,

According to the datasheet for SN65LVD1023, TX clock and RX clock should be spec'd at 50ppm so maximum difference between RX and TX is 100ppm? Or can both RX and TX use 100ppm clock sources?

Also, just wanted to confirm if we have a bit always tied high or always tied low, the receiver won't have a problem aligning to the incoming bit stream. Is it possible that the receiver might get confused for the start of the word?

Thanks in advance!

over 8 years ago

0 Gerardo over 8 years ago

TI__Genius 11280 points

Hello Aaron,
We will check your questions and we will come back to you soon.

Regards,

Gerardo

0 Lee Sledjeski over 8 years ago

TI__Mastermind 43795 points

Hi Aaron,

Yes it is okay for the Rx to use a 100ppm clock source. The Tx clock is usually associated with an FPGA or ASIC of some sort, the clock source driving the ASIC or FPGA and used to generate the TCLK can also be 100ppm.

Regards,

Lee

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SN65LV1023A: Clarifying TX and RX clock spec