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tlk1501: referencing GTXCLK to RXCLK

brian moore
Prodigy 100 points
Part Number: TLK1501
Other Parts Discussed in Thread: CDCM7005

I have a link consisting of 2 TLK1501s. According to the datasheet, each needs its own crystal or clk source to provide GTXCLK.  This means that the uplink and downlink, or GTXCLK and RXCLK,  clock domains at each end of the link will be asychronous to each other. This is problematic in my design, as the 2 clock domains are beating against each other and causing an audible beat note (the design is for digital audio transport). To eliminate this the clocks need to be locked to one another.  Is there a way to derive the GTXCLK of one tlk to the RXCLK it recovers, so that the uplink and downlink clocks are locked to each other and synchronous?  The TLKs are used with a fiber optic link, so there is no way to transport a separate clock between the ends. 

  • 0
    TI__Genius 16150 points
    Hi Brian,

    GTX_CLK is a reference clock that is multiplied by a multiplying clock synthesizer to generate an internal bit rate clock. This bit rate clock is used by the device's clock recovery circuit to lock to an incoming serial data stream. The serial data is converted to parallel, decoded, and outputted along with RX_CLK. Because the TLK1501 uses the GTX_CLK input to generate the RX_CLK output, it is not possible to wrap RX_CLK to GTX_CLK.

    Since the GTX_CLK is actually used as a reference to help the device's clock recovery circuitry generate an RX_CLK output. Also, GTX_CLK needs to be driven by a low-jitter source, which the RX_CLK output is not. (RX_CLK is only there to help latch the output data.)

    If possible I recommend to use a low-jitter oscillator and clock fanout buffer to send a separate GTX_CLK signal to each SerDes.

    For the clocking, one option is the CDCM7005. It can take a VCXO input and synchronize it to the RX_CLK output. The phase offset is typically 1.5 ns, which should be sufficient given the TLK1501's input timing requirements. (A delay on the clock will eat into the hold time. However, the parallel output hold time is ~5.4 ns while the required input hold time is 0.4 ns. This should give plenty of margin to work with.)

    I hope this helps.

    Best Regards,
    Luis