In the DP83822 datasheet it states there are delays the chip can add for TX_CLK and RX_CLK for proper RGMII operation.
In Table 37 it states the internal delay is 3.5ns relative to the data. Why is the delay 3.5ns when the industry standard is 1.5ns of delay?
Is it because the device is only rated for 10/100 that delay can be greater?
Is there a way to chose alternate delay values? Most other PHY's have a way to choose different increments from 0.2ns to 1.0ns up to 3.5ns.
If I don’t use the internal delay, are you suggesting that 10” of trace be added to each clock trace (board delay ~160ps/in) to achieve a delay of only 1.5ns?
Thanks,
MZ