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DP83867IRPAP-EVM: GTX_CLK and TX_CLK usage in DP83867IRPAP

Shanu V
Prodigy 130 points

Part Number: DP83867IRPAP
Other Parts Discussed in Thread: DP83867IR, DP83867E

Hi,

I am using DP83867IRPAP  device in my design.

Initially the plan was to go for MII/GMII/RGMII,  but later the requirement changed to RMII/RGMII.

Is there any PHY which supports RMII  and  RGMII(GbE) ?

I found some devices but, it supports only 100baseT.

As I understand, in RGMII mode, 125MHz GTX_CLK is send by MAC to PHY.

Please answer the below questions for the usage of DP83867IRPAP only for RGMII mode.

1) Do I need to connect any crystal to CLOCK_OUT and CLOCK_IN pins?

2) As the clock from MAC will be connected to GTX_CLK pin,  Can I leave TX_CLK pin open?

3) In RGMII mode, Will the GTX_CLK change the frequency to 25MHz and 2.5MHz to make it work at 100baseT and 10baseT?

4) What is the exact use case of CLK_OUT pin?

  • 0
    TI__Mastermind 19780 points
    Hi Shanu,

    If you are using RGMII mode only, I suggest using the DP83867IRRGZ in the 48 pin package. This device has smaller area, lower power consumption, and is lower cost.

    See my responses to your questions when using DP83867IR in RGMII mode:
    1) Do I need to connect any crystal to CLOCK_OUT and CLOCK_IN pins?
    A 25 MHz crystal must be connected to the XI and XO pins. See the DP83867E RGMII EVM: www.ti.com/.../dp83867ergz-r-evm

    2) As the clock from MAC will be connected to GTX_CLK pin, Can I leave TX_CLK pin open?
    Yes.

    3) In RGMII mode, Will the GTX_CLK change the frequency to 25MHz and 2.5MHz to make it work at 100baseT and 10baseT?
    Yes. In RGMII mode, both clocks run in the following frequency per speed.
    1000M = 125 MHz
    100M = 25 MHz
    10M = 2.5 MHz

    4) What is the exact use case of CLK_OUT pin?
    The CLK_OUT pin is used to provide a 25 MHz reference to another DP83867. This lets engineers use 1 crystal to provide reference to 2 or more DP83867s.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 130 points

    Thanks Rob Rodrigues for the reply.

    1) Is there any PHY from TI which supports RMII and RGMII(GbE) ?
    2) How the 25MHz crystal clock will be used in RGMII mode?
    3) Is it mandatory to use GPIO_0 and GPIO_1??

    Regards,
    Shanu V

  • 0 in reply to Shanu V
    TI__Mastermind 19780 points
    Hi Shanu,

    1) Is there any PHY from TI which supports RMII and RGMII(GbE) ?
    Supporting RMII and RGMII is unusual because RMII is not a 1G capable interface. RGMII supports the speeds 10, 100, 1000
    2) How the 25MHz crystal clock will be used in RGMII mode?
    The 25 MHz crystal is used for creating all the internal clocks for the DP83867. This includes 125 MHz transmit clock for the cable as well as the 125 MHz clocks for RGMII.
    3) Is it mandatory to use GPIO_0 and GPIO_1??
    No.

    Best Regards,