As we all know, a write collision occurs if the SPDR is written while a transfer is in progress, and the WCOL bit is set in the SPI status register. AFAIK, some chips handle write collision in this way: The write operation will not be executed in this case and the transfer continues undisturbed. The writer can check the WCOL bit to see if the writing succeeded.
The write collision above occurs when a transfer is already in progress. Now consider these two situations, while write collisions occur when a transfer is not started yet:
- SPI slave is reading the content of SPDR (data register) (or RX FIFO buffer) to its own memory, at the same time, SPI master started a transfer. Thus, SPI slave will read corrupted (overwritten) data from SPDR.
- SPI salve is writing data from its memory to SPDR (or TX FIFO buffer),at the same time, SPI master started a transfer. Thus, SPI slave will send corrupted data to SPDR.
These two situations usually occur on the slave side, since SPI slave has no control on the timing.
We plan to use TDA2x series (exact chip not determined yet) in our products. Not sure will TI handle the first situation in the same way, and how it handles the latter two situations?
