• State
  • Locked Locked
  • Replies 8 replies
  • Subscribers 32 subscribers
  • Views 1710 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UH948-Q1: DataPathControl 2 register of DS90UH948

Ryuuichi machida
Guru 12620 points
Part Number: DS90UH948-Q1

Hi,

According to datasheet of DS90UH948, "Loaded from remote SER" is decribed in Add 0x28[5:0].

And I confirmed whether these bitfields are changed by using DS90UH949 when bitfield of "override fc config" is "0".

Then, I observed following result.

1. When I write 0x7F to DS90UH949, I observed 0x69 (I expected that 0x3F can be observed in Add 0x28 of DS90UH948).

2. When I write 0x7F to DS90UH949, I observed 0x20 (I expected that 0x00 can be observed in Add 0x28 of DS90UH948).

According to above result, following bitfields are not loaded from SER even though I set Add 0x28[7] of DS90UH948 to 0x0.

* 0x28[5] VIDEO_DISABLED

* 0x28[4] DUAL_LINK

* 0x28[2] I2S DISABLED

* 0x28[1] 28BIT VIDEO

So, Could you please send me correct information about which bitfield of Add 0x28 is loaded from SER when Add 0x28[7] is 0x0 ?

Best Regards,

Machida

  • 0
    TI__Genius 14015 points
    Can you please clarify which register you are writing 0x7F to on the 949?
  • 0 in reply to Jason Blackman
    Guru 12620 points

    Jason-san,

    >Can you please clarify which register you are writing 0x7F to on the 949?

    I'm sorry I mistook the value which I wrote, and will clarify the register as shown below.

    1. When I write 0x7F to Add 0x1A of DS90UH949, I observed 0x69 (I expected that 0x3F can be observed in Add 0x28 of DS90UH948).

    2. When I write 0x00 to Add 0x1A of DS90UH949, I observed 0x20 (I expected that 0x00 can be observed in Add 0x28 of DS90UH948).

    Best Regards,

    Machida

  • 0 in reply to Ryuuichi machida
    Guru 12620 points

    Hi Jason-san,

    Is there any update ?

    Best Regards,

    Machida

  • 0 in reply to Ryuuichi machida
    Guru 12620 points
    Hi Jason-san,

    Sorry for asking several times, but I need feedback about this thread.

    BR,
    Machida
  • 0 in reply to Ryuuichi machida
    TI__Genius 14015 points

    Hi Machida,

    I'm confused about what you're trying to do. Register 0x1A on the 949 only has three bits which are not reserved. The other 5 bits should not be set to 1. 

    Thanks,
    Jason

  • 0 in reply to Jason Blackman
    Guru 12620 points

    Hi Jason-san,

    Thank you for your reply.

     >Register 0x1A on the 949 only has three bits which are not reserved.

    Yes, you are correct. However, according to datasheet of UH948, it seems that Add 0x28[5:0] value comes from SER register.

    So, I would like you to confirm which bitfields are loaded from SER to UH948 in fact.

    (From my experment which I used DS90UH949, at least, bit [5:4] and bit [2:1] of Add 0x28 of UH948 were not loaded from SER register value.)

    Best Regards,

    Machida

  • 0 in reply to Ryuuichi machida
    TI__Genius 14015 points
    Bits [5:4] and [2] are loaded from the serializer but not necessarily from a specific register. It is just based on what the serializer is sending - whether video is sent, if it is single/dual, and whether I2S is present.

    Bit [1] should be loaded from 0x1A like you say, I will have to look into why this is not the case.

    Thanks,
    Jason
  • 0 in reply to Jason Blackman
    Guru 12620 points
    Hi Jason-san,

    >Bits [5:4] and [2] are loaded from the serializer but not necessarily from a specific register. It is just based on what the serializer is sending - >whether video is sent, if it is single/dual, and whether I2S is present.

    I understood that Bits [5:4] and [2] of UH948 indicate information of forward channel (not register infomation).
    In fact, Register information of SER is loaded only Bit[3] and Bits[1:0] to UH948, right ?

    >Bit [1] should be loaded from 0x1A like you say, I will have to look into why this is not the case.
    Is there any information about why this bit is NOT loaded from SER register ?

    Best Regards,
    Machida