• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 32 subscribers
  • Views 900 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI84: PLL_EN_STAT bit never set after enabling it

Anthony Viale
Prodigy 80 points
Part Number: SN65DSI84

Hi team,

I am trying to drive a SN65DSI84 MIPI-to-LVDS Bridge with a STM32F4 microcontroller but I struggle to enable the PLL. My question is the following one : When the 0x0D.0 bit is set (to enable the PLL), is the 0x0A.7 bit is set automatically then I have to wait 3ms for the PLL to lock or is this bit set when the PLL lock ?

I followed the instructions recommended at page 16 for the initialization sequence of the bridge but I added a verification where I check the value of the 0x0A.7 bit until it is set. But since he is never set, I assume that this is the reason why, even if I bypass this verification, my bridge doesn't work (even with only the pattern generator).

Any idea ?

Thanks in advance !

  • 0
    TI__Mastermind 18655 points
    Hello Anthony,

    As a first step, use our DSI Tuner tool to configure the device and please provide the .dsi file. This file can be exported by the utility and will help me to understand your set up. Additionally, I will need you to share the panel datasheet to confirm the set up values.

    Regards,
    Joel
  • 0 in reply to Joel Jimenez0
    Prodigy 80 points

    Hi Joel,

    Thanks a lot for your reply. Your tool has been a real help for me. I solved (I think) my issue thanks to it. I didn't set the right DSI Ch A CLK value (I misunderstood a parameter in the STM32F4 and use the "lane_byte_clock" value instead of the "DDR Clock value". For those who are interested in, see page 75 of the ST Application Note 4860 about the DSI Host).

    Anyway, here are the DSI File from my configuration and the DS file of the panel display. Iin the datasheet, HSYNC, HBP, HFP, VSYNC, VBP and VFP are not provided, only the sum of them (Blanking Times). My value are set arbitrary and I can't confirm they are right.

    DSI and DS Files.zip

  • 0 in reply to Anthony Viale
    TI__Mastermind 18655 points
    Hello Anthony,

    Glad it is resolved.

    You are correct on the blanking period. What matters most is the line time (generated in the output tab) and the clk frequency.

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 80 points

    Thank you Joel.

    I just have one more question since it seems that the parameters are not set correctly for my screen (weird flash). For now I am just using the pattern generator and I am not sure about one thing : is it necessary that the DSI stream is active when using the pattern generator ? I would say "yes" since I use the DSI clock to get the LVDS pixel clock. Moreover, the datasheet says :

    "No DSI data is received while the pattern generator feature is enabled" (p. 14)

    Could you confirm that the DSI stream activation doesn''t interfere with the pattern generator ?

    Regards,

    Anthony.

  • 0 in reply to Anthony Viale
    TI__Mastermind 18655 points
    Hello Anthony,

    In pattern mode, it is no required to have DSI data stream. Only the DSI Clock needs to be provided for LVDS clock generation.

    Regards