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TMDS181: Fails HDMI compliance test (ID8-7: TMDS Jitter Tolerance at 27MHz(480/60p) )

Guru 19785 points
Part Number: TMDS181

Hi Team,

Please help us support customer to pass HDMI compliance test. They are facing a problem that jitter tolerance test is failed at 480/60p video signal using TMDS181. 

TMDS181 is used in the following setting on the customer board.

- Lane swap and Polarity swap are used.
- Setting TMDS181 to Retimer mode across full range since using polarity swap function (Polarity swap can only be used in retimer mode).

Using the TMDS181EVM, this test could be passed. The difference seems to be the swap function that EVM does not use lane swap or polarity swap and set to Auto redriver/retimer mode crossover at 1.0Gbps..

Do you need to use in redriver mode when used in lower data rates ? If you do, polarity swap function would  be restricted in some input video condition.

Sorry to rush you, but, customer is in a hurry that they need to judge their board design by 6/14 (JST) whether TMDS181 could be used with lane and polarity swap function.

Your prompt support would be greatly appreciated.

Best Regards,

Kawai

  • Hi Team,

    Additional information.

    TMDS181 EVM also fails when used in "Retimer mode across full range". Sometime OK, however, when jitter added, video cannot be shown on the monitor.

    When failed "ID8-7: TMDS Jitter Tolerance at 27MHz(480/60p)", TMDS181 shows "TMDS lane Deskew = Not completed" and "Digital lock detect output = Not locked".

    How can we pass "ID8-7: TMDS Jitter Tolerance at 27MHz(480/60p)" ?

    Best Regards,
    Kawai
  • Hi Kawai-san,

    When in retimer mode across the full range, please add this registers writes to the initial configuration.
    This should solve the jitter and image issues.

    Write 0x01 to register 0xFF. To select Page 1
    Write 0x23 to register 0x00. To set A_LOCK_OVR
    Write 0x00 to register 0xFF. To select Page 0

    Regards
  • Hi Moise-san,

    Thanks for your prompt support.
    This setting seems to be working that customer was able pass the jitter tolerance test at 480/60p.
    Here are additional questions from them.

    Q2). What does this bit do and why was the issue solved by setting this bit ?
    It seems to be an override bit of Analog Lock, however, could you please explain what was the problem and how it improved with this setting ?

    Q3). Can the user apply this register setting for all data rates (480/60p - 4K/60p) ?

    Q4). Can this register setting be used for mass production ? (Does TI supports this settings for normal use ?)

    Best Regards,
    Kawai
  • Hi Kawai-san,

    It is an analog lock override, it helps to avoid PLL unlocking at low frequencies.

    yes, it can be used for all data rates

    Yes, it is safe to use it in mass production, this is what we recommend for retimer mode across the full range.

    Regards

  • Hi Moises-san,

    Thank you for the information.

    Q5). When this bit set, I believe Analog Lock is forced as "LOCKED", Analog PLL Lock status is ignored. How come can we ignore this function ?

    We are asked for detail explanation so that customer could understand logically.
    I understand that there is Digital Lock Detect function, too. However, we do not know the mechanism and difference between the two function.

    Q6). Please also tell us if there is any side effect by setting REG 0x23 = 0x00 (A_LOCK_OVR).

    Best Regards,
    Kawai
  • Hi Kawai-san,

    the Analog lock is a step to complete lock, the digital lock is involved too.
    There are no known side effects of setting A_LOCK_OVR
    We can discuss offline if you want

    Regards
  • Hi Moise-san,

    Thanks. Please allow me to discuss offline a little bit more.

    Best Regards,
    Kawai