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DS90UH948-Q1: Default register value for Port 1

Ryuuichi machida
Guru 12845 points
Part Number: DS90UH948-Q1


Hi,

I would like you to confirm about default value of Port 1 register.

According to datasheet, some registers of DS90UH948 should be set Port 0 and Port 1 individually depending on usecase.

I understood that default value of these registers for Port0 and Port1 are same because there is no desciption about default value for port 1 especially.

However, when I checked the default value when I set 0x34[1:0] to 0b11, I observed un-expected value for folloing register.

1. When 0x34[1:0]=0b01, (Read value is for Port 0)
0x1D 0x10
0x1E 0x00
0x1F 0x00
0x56 0x00

2. When 0x34[1:0]=0b11, (Read value is for Port 1)
0x1D 0x13
0x1E 0x33
0x1F 0x03
0x56 0x08

I expected that I can see same value for above "2".
However, the result was different.

So could you please confirm about default register value for Port 1 ?

Best regards,

Machida

  • 0
    Guru 12845 points

    Hi,

    Could you please send me your feedback ?

    Best Regards,

    Machida

  • 0 in reply to Ryuuichi machida
    TI__Genius 12705 points
    Hello,
    Please do not set both Port select bits at the same time, set either bit 0 or bit 1 and clear the other bit, 0x34[10] = 01 or 0x34[1:0] = 10.
  • 0 in reply to Liam Keese
    Guru 12845 points

    Hi, Liam-san,

    Thank you for your reply.

    >Please do not set both Port select bits at the same time, set either bit 0 or bit1 and clear the other bit, 0x34[10] = 01 or 0x34[1:0] = 10.

    According to UH948 datasheet, there is following description.

    "Setting the PORT1_SEL and PORT0_SEL bit will allow a read of the register for the selected port. If both bits are

    set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing simultaneous

    writes to both ports if both select bits are set."

    So, I'm not sure why you describe as shown above.

    Do you have plan to change description about above sentence ?

    And also, do you think that this phenomenon influences above setting (both port select are set) ?

    Best Regards,

    Machida 

  • 0 in reply to Ryuuichi machida
    TI__Genius 14015 points
    Hi Machida,

    I double-checked these on our EVM and your values are correct. The datasheet needs to be updated with these default values for D_GPIO. I've logged it as a bug to be fixed.

    It's fine if you have both PORT1_SEL and PORT0_SEL set at the same time.

    Thanks,
    Jason
  • 0 in reply to Jason Blackman
    Guru 12845 points

    Hi Jason-san,

    Thank you for your reply and response.

    >I double-checked these on our EVM and your values are correct. The datasheet needs to be updated with these default values for D_GPIO. I've logged it as a bug to be fixed.

    According to your comment, I understood that default value for following registers of PORT0 and PORT1 were different. And you will describe each default value for following registers in furure datasheet.

    Is my understanding correct ?

    0x1D GPIO0 Config
    0x1E GPIO1_2 Config
    0x1F GPIO3 Config
    0x56 CML OUTPUT ENABLE

    If you have other registers which you will describe each default value, please let me know.

    Best Regards,

    Machida

  • 0 in reply to Ryuuichi machida
    Guru 12845 points
    Hi Jason-san,

    Is there any update ?

    BR,
    Machida