Part Number: DS92LV1212A
We're considering using the "DSLV1212A 16-40 MHz 10-bit bus LVDS random lock deserializer with embedded clock recovery", paired with the DS92LV1021A serializer, for SPI data with multiple chip selects.
(This would be for SPICLK, SPISIMO, and multiple SPICSn; for SPISOMI we'd most likely use a dedicated non-serialized diff driver.)
In particular, we're thinking of doing this "open-loop", where we don't initiate SYNC patterns, but instead depend upon the 1212A's random lock initialization and resynchronization.
We'd like to avoid the "false lock" possibility, by avoiding the repetitive multi-transition (RMT) patterns described in the data sheet.
The RMT danger looks to be closely tied to how adjacent DIN bit behave with respect to each other. In particular, holding one bit low while the adjacent one is held high. This will happen by definition in our system where we have multiple bits used for SPI chip selects.
What can we do to minimize or characterize this RMT risk? We're likely to only be using 4 or so chip selects, which will leave 4 or so bits unused. Normally we would consider it best practice to tie those bits to ground. To avoid RMT, are we better off connecting them to some kind of varying signal?
Once we've successfully syncronized, what risk is there that RMT patterns in our data could cause us to lose lock?
When we're not in the middle of an SPI transaction, we could potentially ensure that all 10 bits are high. What is the worst case time for the DS92LV1212A to resynchronize when all 10 bits to the DS92LV1021A are held high?
--thx
