Hi,
Let me ask you some basic questions as below?
Q1) Chip select
According to the datasheet, in case of using multiple DS32EL0421,
about 1st chip, the CS signal is from CPU and about after 2nd device, using GPIO0.
By connecting GPIO0, we can reduce the number of CS signals.
Or is there any demerit to use this way?
Q2) Demerit of "Scrambler and NRZI encorder"
Is there any demerit to use this encorder?
Q3) Input of Tx4+/- pin in case of using "DC-BALANCE encorder"
In case of using this encorder, what should we do for Tx4+/- pin?
Should we do "pull-down" for Tx4+/- pin, for example?
Q4) Data payload in case of using DC-Balance encording
There describes "If the integrated DC-balance encoding is enabled, the maximum data
payload achievable is 2.5 Gbps" on the data sheet page1.
Could you tell me how to calculate this number (2.5GHz)?
When DC-balance encording is enabled, the paldata lane unmber becomes "4". (TxIN0-3)
The total taken data is 16bit but extended to 20bit by "8b/10b" conversion. (from datasheet page12)
So the output clock is max 3.125GHz(@Tx=312.5MHz), I think....
I appreciate your support very much.
Best Regards,
