SN65DSI86-Q1: link training fails on SN65DSI86 ?

Robin singh1

Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: SN65DSI86

HI All,

I am trying to bring up JDI 4K edp display on qulacomm(msm8996) platform by using SN65DSI86. here is my panel parameters:

H x V(3840 x 2160)

HPW = 32 , VPW = 8 , HBP = 40 , HFP = 8, VBP = 6 , VFP = 48

Panel Support : ASSR .
Number of lane connected to eDP panel from eDP bridge = 4 (0 1 2 3)
Number of DSI channel commected to App processor 2 (CHA and CHB) (DSI laneper channel =4)

I am able to communicate with the Panel via I2C over AUX channel and read DPCD and EDID information correctly but link tanning fails and the error message i get is:

register 0xF8 = 0x12, which indicate this error :( LT_EQ_LPCNT_ERR. This field is set whenever link training fails in the channel equalization phase RCU due to the loop count being greater than five)

I do have a few question about the eDP bridge :

1) Do you have any recommended sample code for eDP panel bringup , i am refereing now from datasheet page 69?

2) Do i need to do Video parameter setting before link tranning ? Does video video parameter setting is required for link trainning?

3) should there be any data comming from DSI input port ( clock or data ) before starting link tranning ?

3) what are the recommend DSI command for configureing eDP register via DSI? I am using 0x29(generic long write) for writting registers , is that correct ?

4) what is the recommend command type for reading the registers via DSI ?

5) Do you have DSI initilization command set for eDP bridge ?

=========================== my code for eDP bridge configutaion via I2C =====

dsi86_write_register( 0x59, 0x93); //DSI lane assignment.For customer board = 0x93 
mdelay(7);
dsi86_write_register( 0x0a, 0x06); //27 Mhz ref clock 
mdelay(7);
dsi86_write_register( 0x10, 0x80);// Left right pixel / Dual channel DSI receiver/ CHA -4 lanes /CHB - 4 lanes 
mdelay(7);
dsi86_write_register( 0x12, 0x6F); // bit clock = 8* byte0 clk ; 1112.72 Mhz / 2 = //DSICH-A clock range //556.18 Mhz by JDI 4K 
mdelay(7);
dsi86_write_register( 0x13, 0x6F); //; //DSICH-A clock range //556.18 Mhz by JDI 4K 
mdelay(7);
dsi86_write_register( 0x5a, 0x85); //for customer board =0x85
mdelay(7);
/*Link Tranning */
dsi86_write_register( 0x0d, 0x00); // disable PLL en
mdelay(7);
dsi86_write_register( 0x93, 0x30); //24
mdelay(7);
dsi86_write_register( 0x94, 0xE0); //80 
mdelay(7);
dsi86_write_register( 0x0d, 0x01); // enable PLL en
mdelay(150);


val =0;
for(i = 0; i < 10; i++){
dsi86_read_register( 0x0A, &val);
if ((val & 0x80)) {
break;
}
}
if (i >= 10) {
pr_err("\n >>>>>>>>>>>>>>>>>>>>>>>>>>> SN65DSI86 PLL not ready!\n");
ret = -1;
}
//ReadDPCDPara(); reading these works correctly
mdelay(7);
//sn65dsi86_read_edid(); this is also correct and matching with datasheet.

mdelay(15);
dsi86_write_register( 0x95, 0x00);
mdelay(7);
dsi86_write_register( 0xF4, 0xFF);
mdelay(7);

dsi86_write_register( 0x64, 0x01);
mdelay(7);
dsi86_write_register( 0x74, 0x00);
mdelay(7);
dsi86_write_register( 0x75, 0x01);
mdelay(7);
dsi86_write_register( 0x76, 0x0a);
mdelay(7);
dsi86_write_register( 0x77, 0x01);
mdelay(7);
dsi86_write_register( 0x78, 0x81);
mdelay(10);

for(i=0;i<5;i++) {
dsi86_write_register( 0x96, 0x0a);
mdelay(110);
val =0;
dsi86_read_register( 0x96, &val);
pr_err("\n >>>>>>>>>>>>>>>>>>>>>> 0x96 = %X\n", val);
val =0;
mdelay(7);
dsi86_read_register( 0xF8, &val);
pr_err(">>>>>>>>>>>> 0xF8 = %X\n", val);
if ((val & 1) == 1) {
pr_err("\n ======== ## Link setup success ##\n");
break;
}else
pr_err("\n ====## Link setup FAILED ##\n");
}
mdelay(7);
dsi86_write_register(0x3c, 0x18 | 1);

=============================================================================
My reg DUmp
=============================================
[ 26.566435] Dump sn65dsi86 register
[ 26.568928] 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
[ 26.580167] -------------------------------------------------------
[ 26.580173] 00 | 36 38 49 53 44 20 20 20 02 00 86 00 00 01 00 00
[ 26.580176] 10 | 80 00 6f 6f 00 00 00 00 00 00 00 00 00 00 00 00
[ 26.580180] 20 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 26.580183] 30 | 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00
[ 26.580186] 40 | 01 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
[ 26.580189] 50 | 00 00 00 00 00 00 20 00 40 93 85 00 10 00 90 00
[ 26.580192] 60 | a0 60 a4 00 00 77 30 30 00 00 00 00 00 00 00 00
[ 26.580196] 70 | 00 00 00 00 00 01 02 01 80 71 17 50 4d 31 33 33
[ 26.580199] 80 | 4d 33 38 35 41 20 20 00 73 1f 7c f0 c1 07 1f 7c
[ 26.580202] 90 | f0 c1 07 b0 e0 0c 00 04 01 00 00 00 00 00 00 00
[ 26.580205] a0 | 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 26.580208] b0 | 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c
[ 26.580212] c0 | 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 26.580215] d0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 26.580218] e0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 26.580221] f0 | 00 00 00 00 01 02 00 00 12 00 00 00 00 00 00 00

here is the DPCD /EDID data with registers dump from SN65DSI86
================================================
The DPCD 0 byte = 0x12
The DPCD 1 byte = 0x14

The DPCD 2 byte = 0xc4
The DPCD 3 byte = 0x41

The DPCD 4 byte = 0x00
The DPCD 5 byte = 0x00

The DPCD 6 byte = 0x01
The DPCD 7 byte = 0x40

The DPCD 8 byte = 0x02
The DPCD 9 byte = 0x5f

The DPCD 10 byte = 0x00
The DPCD 11 byte = 0x00

The DPCD 12 byte = 0x00
The DPCD 13 byte = 0x0b

The DPCD 14 byte = 0x01
The DPCD 15 byte = 0x00

--- EDID information from panel ---

The EDID 0th byte = 0x00
The EDID 1th byte = 0xff
[ 21.339686]
The EDID 2th byte = 0xff
[ 21.351239]
The EDID 3th byte = 0xff
[ 21.362431]
[ 21.362431] The EDID 4th byte = 0xff
The EDID 5th byte = 0xff

[ 21.398566]
[ 21.398566] The EDID 6th byte = 0xff
The EDID 7th byte = 0x00
[ 21.421521]
[ 21.421521] The EDID 8th byte = 0x28
The EDID 9th byte = 0x89
[ 21.443122]
[ 21.443122] The EDID 10th byte = 0x5a
The EDID 11th byte = 0x38
[ 21.465167]
The EDID 12th byte = 0x00
[ 21.476365]
[ 21.476365] The EDID 13th byte = 0x00
The EDID 14th byte = 0x00
[ 21.498062]
[ 21.498062] The EDID 15th byte = 0x00

[ 21.547728]
[ 21.547728] The EDID 0th byte = 0x00
The EDID 1th byte = 0x1b
[ 21.569216]
[ 21.569216] The EDID 2th byte = 0x01
The EDID 3th byte = 0x04
[ 21.590675]
[ 21.590675] The EDID 4th byte = 0xa5
The EDID 5th byte = 0x1d
[ 21.612099]
[ 21.612099] The EDID 6th byte = 0x11
The EDID 7th byte = 0x78
[ 21.634020]
[ 21.634020] The EDID 8th byte = 0x03
The EDID 9th byte = 0xc9
[ 21.655447]
[ 21.655447] The EDID 10th byte = 0x33
The EDID 11th byte = 0xa4
[ 21.677117]
[ 21.677117] The EDID 12th byte = 0x53
The EDID 13th byte = 0x4d
[ 21.699301]
[ 21.699301] The EDID 14th byte = 0x99
The EDID 15th byte = 0x27
[ 21.713542]
[ 21.713542]
The EDID 0th byte = 0x0e
[ 21.773080]
[ 21.773080] The EDID 1th byte = 0x4e
The EDID 2th byte = 0x52
[ 21.794721]
[ 21.794721] The EDID 3th byte = 0x00
The EDID 4th byte = 0x00
[ 21.816381]
[ 21.816381] The EDID 5th byte = 0x00
The EDID 6th byte = 0x01
[ 21.838423]
[ 21.838423] The EDID 7th byte = 0x01
The EDID 8th byte = 0x01
[ 21.859857]
[ 21.859857] The EDID 9th byte = 0x01
The EDID 10th byte = 0x01
[ 21.881381]
[ 21.881381] The EDID 11th byte = 0x01
The EDID 12th byte = 0x01
[ 21.903127]
[ 21.903127] The EDID 13th byte = 0x01
The EDID 14th byte = 0x01
[ 21.924775]
[ 21.924775] The EDID 15th byte = 0x01

[ 21.974143]
[ 21.974143] The EDID 0th byte = 0x01
The EDID 1th byte = 0x01
[ 21.995530]
[ 21.995530] The EDID 2th byte = 0x01
The EDID 3th byte = 0x01
[ 22.016893]
[ 22.016893] The EDID 4th byte = 0x01
The EDID 5th byte = 0x01
[ 22.038662]
[ 22.038662] The EDID 6th byte = 0x25
The EDID 7th byte = 0xcc
[ 22.059934]
[ 22.059934] The EDID 8th byte = 0x00
The EDID 9th byte = 0x50
[ 22.081187]
[ 22.081187] The EDID 10th byte = 0xf0
The EDID 11th byte = 0x70
[ 22.102584]
[ 22.102584] The EDID 12th byte = 0x3e
[ 22.119121]
[ 22.119121] The EDID 13th byte = 0x80
[ 22.129852]
[ 22.129852] The EDID 14th byte = 0x08
[ 22.134666]
[ 22.134666] The EDID 15th byte = 0x20
[ 22.184869]
[ 22.184869]
[ 22.194352]
[ 22.194352] The EDID 0th byte = 0x08
[ 22.206468]
[ 22.206468] The EDID 1th byte = 0x0c
[ 22.218577]
[ 22.218577] The EDID 2th byte = 0x26
[ 22.231111]
[ 22.231111] The EDID 3th byte = 0xa5
[ 22.243193]
[ 22.243193] The EDID 4th byte = 0x10
[ 22.255277]
[ 22.255277] The EDID 5th byte = 0x00
[ 22.267546]
[ 22.267546] The EDID 6th byte = 0x00
[ 22.279674]
[ 22.279674] The EDID 7th byte = 0x1a
[ 22.291782]
[ 22.291782] The EDID 8th byte = 0x51
[ 22.303837]
[ 22.303837] The EDID 9th byte = 0xa3
[ 22.315895]
[ 22.315895] The EDID 10th byte = 0x00
[ 22.328448]
[ 22.328448] The EDID 11th byte = 0x50
[ 22.340582]
[ 22.340582] The EDID 12th byte = 0xf0
[ 22.349749]
[ 22.349749] The EDID 13th byte = 0x70

[ 22.357211]
[ 22.357211] The EDID 14th byte = 0x3e

[ 22.360295]
[ 22.360295] The EDID 15th byte = 0x80
[ 22.378021]

[ 22.408199]
[ 22.408199] The EDID 0th byte = 0x08
[ 22.413878]
[ 22.413878] The EDID 1th byte = 0x20

[ 22.421920]
[ 22.421920] The EDID 2th byte = 0x08
[ 22.427564]
[ 22.427564] The EDID 3th byte = 0x0c

[ 22.437803]
[ 22.437803] The EDID 4th byte = 0x26

[ 22.448051]
[ 22.448051] The EDID 5th byte = 0xa5
[ 22.456332]
[ 22.456332] The EDID 6th byte = 0x10
[ 22.463701]
[ 22.463701] The EDID 7th byte = 0x00
[ 22.471075]
[ 22.471075] The EDID 8th byte = 0x00
[ 22.478192]
[ 22.478192] The EDID 9th byte = 0x1a
[ 22.482975]
[ 22.482975] The EDID 10th byte = 0x00

[ 22.496429]
[ 22.496429] The EDID 11th byte = 0x00
[ 22.503941]
[ 22.503941] The EDID 12th byte = 0x00
[ 22.509769]
[ 22.509769] The EDID 13th byte = 0xfe
[ 22.515552]
[ 22.515552] The EDID 14th byte = 0x00
[ 22.518742]
[ 22.518742] The EDID 15th byte = 0x4a

[ 22.568910]
[ 22.568910] The EDID 0th byte = 0x44
[ 22.577726]
[ 22.577726] The EDID 1th byte = 0x49
[ 22.577780]
[ 22.577780] The EDID 2th byte = 0x20

[ 22.592511] The EDID 3th byte = 0x20
[ 22.600493]
[ 22.600493] The EDID 4th byte = 0x20
[ 22.601642]
[ 22.601642] The EDID 5th byte = 0x20
[ 22.616382]
[ 22.616382] The EDID 6th byte = 0x20
[ 22.624322]
[ 22.624322] The EDID 7th byte = 0x20
[ 22.634615]
[ 22.634615] The EDID 8th byte = 0x20
[ 22.642104]
[ 22.642104] The EDID 9th byte = 0x20
[ 22.648251]
[ 22.648251] The EDID 10th byte = 0x20
[ 22.653992]
[ 22.653992] The EDID 11th byte = 0x20
[ 22.659678]
[ 22.659678] The EDID 12th byte = 0x00
[ 22.667831]
[ 22.667831] The EDID 13th byte = 0x00
[ 22.673557]
[ 22.673557] The EDID 14th byte = 0x00

[ 22.680497] The EDID 15th byte = 0xfe
[ 22.689614]

[ 22.732112]
[ 22.732112] The EDID 0th byte = 0x00
[ 22.736766]
[ 22.736766] The EDID 1th byte = 0x4c
[ 22.744477]
The EDID 2th byte = 0x50

The EDID 3th byte = 0x4d
[ 22.766075]
[ 22.766075] The EDID 4th byte = 0x31
[ 22.785637]
[ 22.785637] The EDID 5th byte = 0x33
[ 22.798407]
[ 22.798407] The EDID 6th byte = 0x33
[ 22.810557]
[ 22.810557] The EDID 7th byte = 0x4d
[ 22.822628]
[ 22.822628] The EDID 8th byte = 0x33
[ 22.834727]
[ 22.834727] The EDID 9th byte = 0x38
[ 22.846816]
[ 22.846816] The EDID 10th byte = 0x35
[ 22.859379]
[ 22.859379] The EDID 11th byte = 0x41
[ 22.871811]
[ 22.871811] The EDID 12th byte = 0x20
[ 22.884128]
[ 22.884128] The EDID 13th byte = 0x20
[ 22.885383]
[ 22.885383] The EDID 14th byte = 0x00
[ 22.885383]
[ 22.908736]
The EDID 15th byte = 0x73

please give me your feedback ?

Thanks

Robin Singh

over 8 years ago

0 Joel Jimenez0 over 8 years ago

TI__Mastermind 18655 points

Hello Robin,

I'm checking your questions and looking for a script that you can use as a reference.

Meanwhile, take a look at the attached file which contains some more examples of how to configure the device.

0003.DSI86_SW_EXAMPLES.pdf

0 Robin singh1 over 8 years ago in reply to Joel Jimenez0

Prodigy 150 points

HI Joel,

Thank you for your response.

I have already referred above pdf from your other post. I am configuring the SN65DSI86 upto the link training only and getting 0xF8 = 0x12 error.

please take a look on my other questions too.

Do you suggest some other check points , which i need to verify on my board ?

Thanks

Robin Singh

0 Joel Jimenez0 over 8 years ago in reply to Robin singh1

TI__Mastermind 18655 points

Robin,
I suggest you adjusting the LUT parameters to optimize DSI86’s VOD and PRE-emphasis levels used in Link Training. LUT is located in registers B0h thru C3h.
Also clear the interrupt and then read back to see if error only occurs once or if it occurs all the time.
Could you try disabling the enhanced framing? By writing 0x8D to address 0x5A followed by 0x89.
Regards

0 Robin singh1 over 8 years ago in reply to Joel Jimenez0

Prodigy 150 points

Thanks Joel for your answers . I will give it a try and come back with my result.

0 Robin singh1 over 8 years ago in reply to Robin singh1

Prodigy 150 points

Hi Joel,

I tried disabling enhanced framing and clearing interrupt but no good result, link training still fails.

From clearing the interrupt status register, i see first time SEND_INT bit seem to 1 and after that in all the try it is '0'.

i also tried to read the below registers from panel during link training phase and see the below results:

0x000202h value is 0x75
0x000203h value is 0x57
0x000204h value is 0x00

Regarding optimizing LUT parameter for VOD and pre-emphasis, i am bit confused, for changing VOD level2 and pre-emphasis level 2,
i made the below change , is that right?

Register 0x93 = 0xB4 (DP_PRE_EMPHASIS = level 2 & DP_NUM_LANES = 4 , 3750 Down spread clock spread disable)
Register 0x94 = 0XC2 ( DP_TX_SWING Voltage swing level 2 , DP_DATARATE 4.32 Gbps )

then i moved to changed 0xB8~ 0xbb = 0x9c(default was 0x0C and 5C) ( V2_P0_PRE. = 5.19 db V2_P0_VOD = 800mV)

Now if i want to change to level 3 for VOD and pre-emphasis, i need choose the register set from 0xbc thru 0xbf and configure it , is that right ?
Do you have any doc /script/sample code , which can help me to understand better to optimized LUT registers?

Thanks
Robin Singh

int ret =0,i=0 ;
        unsigned char val;
        pr_err("\n %s\n", __func__);
        dsi86_write_register( 0x09, 1);
        mdelay(100);
        dsi86_write_register( 0x5a, 0x00);
        mdelay(7);
        dsi86_write_register( 0x0a, 0x06);
        mdelay(5);
        dsi86_write_register( 0x10, 0x80);
        mdelay(5);
        dsi86_write_register( 0x12, 0x6F); //
        mdelay(5);
        dsi86_write_register( 0x59, 0x93);
        mdelay(5);
        dsi86_write_register( 0x5a, 0x8D);
        mdelay(5);
        dsi86_write_register( 0x5a, 0x89);
        mdelay(5);

        dsi86_write_register( 0x93, (2<< 6) | // DP pre emphasis lv0
                                    (3<< 4) | // DP 4 lanes
                                    (2<< 1) | // Downspread 3750ppm
                                    (0<< 0)); // disable ssc
        mdelay(5);
        val =0 ;
        dsi86_read_register( 0x93, &val);
        pr_err("\n DP_PRE_EMPHASIS & DP_NUM_LANES = %X\n",val);
        val =0;
        mdelay(5);
        dsi86_write_register(0x94, (6 << 5) | // 2.7 Gbps
                                   (0 << 2) | // 61ps
                                   (2 << 0)); // DP_TX_SWING level =2 /3/1
        mdelay(5);
dsi86_read_register( 0x94, &val);
        pr_err("\n DP_TX_SWING , DP_DATARATE  = %X\n",val);
        dsi86_write_register( 0xe5, 0x01);
        mdelay(5);
        update_vod_pre_emphasis_levels();
        dsi86_write_register( 0x0d, 0x01); // enable PLL en
        mdelay(150);
        pr_err("\n ---- waiting for PLL ready --- \n");
        val =0;
        for(i = 0; i < 10; i++){
                dsi86_read_register( 0x0A, &val);
                if ((val & 0x80)) {
                        break;
                }
        }
        if (i >= 10) {
                pr_err("\n >>>>>>>>>>>>>>>>>>>>>>>>>>>    SN65DSI86 PLL not ready!\n");
                ret = -1;
        }
        mdelay(15);
        dsi86_write_register( 0x95, 0x00);
        mdelay(7);
        dsi86_write_register( 0x64, 0x01);
        mdelay(7);
        dsi86_write_register( 0x74, 0x00);
        mdelay(7);
        dsi86_write_register( 0x75, 0x01);
        mdelay(7);
        dsi86_write_register( 0x76, 0x0a);
        mdelay(7);
        dsi86_write_register( 0x77, 0x01);
        mdelay(7);
        dsi86_write_register( 0x78, 0x81);
        mdelay(10);
        for(i=0;i<5;i++) {
                dsi86_write_register( 0x96, 0x0a);
                mdelay(30);
                val =0;
                dsi86_read_register( 0x96, &val);
                pr_err("\n >>>>>>>>>>>>>>>>>>>>>>  0x96 = %X\n", val);
                        val =0;
                        mdelay(7);
                        dsi86_read_register( 0xF8, &val);
                        pr_err(">>>>>>>>>>>> 0xF8 = %X\n", val);
                        if ((val & 1) == 1) {
                                pr_err("\n    ======== ## Link setup success ##\n");
                                break;
                        }else
                                pr_err("\n ====## Link setup FAILED ##\n");
                mdelay(5);
                val =0;
                dsi86_read_register(0xF4, &val);
                mdelay(5);
                pr_err("\n SEND_INT(0xF4) is  = %X\n", val);
                ReadDPCDPara_xxxxxxH(0x00,0x02,0x02);
                ReadDPCDPara_xxxxxxH(0x00,0x02,0x03);
                ReadDPCDPara_xxxxxxH(0x00,0x02,0x04);

                dsi86_write_register( 0xF4, 0xFF);
                mdelay(7);
        }
        mdelay(5);
        //ReadDPCDPara();
        return 0;

0 Joel Jimenez0 over 8 years ago in reply to Robin singh1

TI__Mastermind 18655 points

Hello Robin,

Sorry for the delay in our response. There are a couple of things I wanted to clarify:

According to the EDID the panel supports a pixel clock of 522.61MHz. At 18bpp (the DSI86 does not support 24bpp for this resolution) the stream bit rete will be:

Stream Bit Rate = PixelClock × bpp

Stream Bit Rate = 522.61× 18

Stream Bit Rate = 9.4069 Gbps

To determine the minimum required DSI clock frequency to support the stream bit rate of the eDP panel. For 18 bpp, the calculation for determining the DSI clock frequency is as follows:

Min Required DSI Clock Frequency = StreamBitRate / (Min_Number_DSI_Lanes × 2)

Min Required DSI Clock Frequency = 9406.9/ (8 × 2)

Min Required DSI Clock Frequency = 587.92 MHz

In order to support the panel stream bit rate, the SN65DSI86 eDP interface must be programmed so that the total eDP data rate is greater than the stream bit rate.

For your application the eDP data rate is calculated as:

eDP Total Bit Rate = #_of_eDP_Lanes × DataRate × 0.80

eDP Total Bit Rate = 4 × 2.7 Gbps × 0.80

eDP Total Bit Rate = 8.64 Gbps (which is not enough to support the total stream bit rate)

However, the eDP panel DPCD registers indicates that a data rate of 5.4 Gbps per lane is supported. So, you will need to configure the DSI86 to support 5.4 Gbps and 4 lanes.

Please, take a look at the attached video register config. REG CONFIG.zip

Interface

Interface forum

SN65DSI86-Q1: link training fails on SN65DSI86 ?