my design as follows ：CMOS（MT9V032）+DS90UB913+DS90UB914；
During the hardware test，I use a Altera Cyclone IV FPGA to view the signals as follows.
up_vs：the output vsync of ds90ub914
up_line_valid：the output hsync of ds90ub914
up_exposure：the output pass of ds90ub914
up_reset：the output lock of ds90ub914
up_dout：the output 8-bits data of ds90ub914
up_pixclk：the output pixclk of ds90ub914
burst_line：the line counts of a frame
During the test，I did not do any configrations of ds90ub913 and ds90ub914. Ds90ub914 configed as 12-bit low frequency（cmos output 320*240, which the pixclk is about 13MHZ,60fps）, through the signalwave, the sync and the control signals such as vsync,hsync,lock,pass,pixclk are all correct, but the image date is always 0x20 during the row time,and change to be 0x00 during the row blank time.
My questions are:
1, what reasons maybe cause the problem?
2, Should the registers of ds90ub913 and ds90ub914 be configured?（cmos will be configured by fpga, not through ds90ub913 and ds90ub914）
