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TMDS181: SCL/SDA lines are not working normally in a Tx/Rx application

Gary Fong
Prodigy 50 points
Part Number: TMDS181
Other Parts Discussed in Thread: TCA9617B

In my application, there is a TMDS181 in the Tx and Rx units.  When the Tx was operating standalone, the SCL/SDA lines worked normally.  The Rx also worked normally when operating standalone.

However, when the Tx was connected to the Rx per the application setup below, the video generator was not able to read the EDID reliably from the monitor.  At times the video generator experienced a DDC bus timeout when trying to read the EDID.

Application setup:

Video generator => (Tx) TMDS181 => cable => (Rx) TMDS181 => Monitor

Tx TMDS181 configuration: Lane swap enabled, Polarity swap enabled, Retimer mode across full range 250 Mbps to 6 Gbps; Active DDC block bypassed per Figure 35 of datasheet.

Rx TMDS181 configuration: Lane swap enabled, Polarity swap enabled, Retimer mode across full range 250 Mbps to 6 Gbps; connected to Active DDC block.

Should the SCL/SDA lines be able to operate normally in this application?

  • 0
    TI__Guru 60870 points
    Hello Gary,

    The issue could be with the Video Generator source not supporting the I2C clock stretching implemented by the TMDS181. This will not be an issue with the TMDS181 on the TX side since the DDC is implemented in snoop mode, but this is probably a concern with the TMDS181 in the RX side since DDC is being routed through the TMDS181. I would recommend putting the TMDS181 in the RX side in DDC snoop mode, if the capacitance on the DDC lines is a concern, I would recommend implementing the TCA9617B.

    Regards,
    JMMN
  • 0 in reply to JMMN
    Prodigy 50 points

    Hi JMMN,

    Please confirm that setting 0Bh bit-0 to 0 (DDC training enabled) puts the TMDS181 in DDC snoop mode.  If that is the case, then the TMDS181 in the Rx was in DDC snoop mode.

    What I have observed is that when the Tx and Rx are powered up (without video generator or monitor connected), the SCL_SNK, SDA_SND and SDA_SRC signals are Low in the Rx TMDS181.  When that happened, the DDC bus did not work correctly.

    When the Tx and Rx powered up and the SCL_SNK, SDA_SND and SDA_SRC signals were High in the Rx TMDS181, then the DDC worked normally.

    What can cause the SCL_SNK, SDA_SND and SDA_SRC signals to come up in the Low state?  Is there something wrong with the Active DDC Block?

    Best regards,

    Gary

  • 0 in reply to Gary Fong
    TI__Guru 60870 points
    Hi Gary,

    The SCL/SDA pins should not power up and stay low since they are open drain signals. This would indicate that they are being driven low somewhere in the system. What pullups are installed on these lines? To which voltage are the pullups referenced?

    Due to some HDMI sources not supporting I2C clock stretching, we recommend that DDC be implemented in snoop mode. Snoop mode is not set by the register. Snoop mode means that SDA_SRC and SCL_SRC are tied low and the DDC lines are only routed by the SDA_SNK and SCL_SNK lines.

    Regards,
    JMMN
  • 0 in reply to JMMN
    Prodigy 50 points

    Hi JMMN,

    It turns out that the SCL/SDA pins powering up low was caused by OE being asserted too early.  After adding some delay before asserting OE, the SCL/SDA lines powered up high.

    Per section 8.4.3 of the data sheet, I thought snoop mode was related to DDC training and register 0Bh bit-0 which enables it.  Can you clarify the function of DDC training?

    Best regards,

    Gary

  • 0 in reply to Gary Fong
    TI__Mastermind 23815 points
    Hi Gary,

    It's great the DDC pins are working correctly now, let me elaborate on the DDC training feature.
    For HDMI2.0 the relation between the data rate en the clock frequency changes from 1/10 to 1/40, this is signaled through DDC and monitored by the TMDS181 to configure itself accordingly. This change is updated in register TMDS_CLOCK_RATIO_STATUS(0x0B[1]).

    In a sink application, this is the connection on DDC(add pull-ups accordingly)
    DDC normal mode:
    SCL_SNK/SDA_SNK connect to HDMI receiver
    SCL_SRC/SDA_SRC connect to HDMI connector(plus level shifter)

    DDC snoop mode:
    SCL_SNK/SDA_SNK connect to HDMI receiver and HDMI connector(no level shifter is needed)
    SCL_SRC/SDA_SRC tied to GND.

    The TMDS181 implements clock stretching on DDC, which may cause interoperability issues, the snoop mode is recommended to avoid the clock stretching of DDC and still monitor the TMDS_CLK ratio.

    Regards