TLK10031: TLK10031 - About 10GKR/1G-KX mode

Hi Kanemaru,

The device is configured in 10GBASE-KR by default. Hence if you don't configure the device through MDIO, you jus need to perform a hardware reset. On the other hand, I suggest configure it through MDIO since the TLK is a complex device and several registers would need to be adjusted (equalization, data switch, etc.) according every system (AC losses, length of traces, among others).


Best Regards,
Luis Omar Moran
High Speed Interface
SWAT Team

Hi Luis-san,

Thank you for your prompt reply.

I will report this information to our customer.

Regards,

Kanemaru

Hi Luis-san,

 

I have one more question.

Our customer would like to use “REFCLK 156.25MHz” for “10GBASE-KR Mode”.

According to the datasheet, SERDES PLL Multiplier of High speed side default setting is 20x and Low speed side default setting is 10x.

Therefore, I understand that TLK10031 can’t communicate “10GBASE-KR Mode” if they use “REFCLK 156.25MHz” at the default .

Because, they have to set the following conditions.

 

 

Is my understanding correct?

 

Regards,

Kanemaru

Hi Kanemaru,

Your assumption is correct. Customer needs to set the SERDES PLL Multiplier (HS side) to 16.5 since the default value is 20. This is done through the register 0x1E.0002 bits [3:0].

Regards,
Luis

Hi Luis-san,

 

Thank you for your prompt reply.

I understand. Thank you very much.

 

Regards,

Kanemaru

Hi Luis-san,

 

I have one more question.

Our customer would like to use “REFCLK 156.25MHz” for “10GBASE-KR Mode”.

Therefore, they change “HS_PLL_MULT [3:0]” from “1101(default)” to “1100” and don’t change the other resisters(so the other resisters are default).

Is there the other register that they have to change?

So, could you please let us know if you have the recommended setting for this use case?

 

< Background>

Of course, they understand that they must change those registers related to the signal quality(for example, HS_SERDES_CONTROL_1/2/3) to optimize the signal conditions.

They will confirm this registers if a prototype model is completed.

Therefore, they would like to know if there is those registers that they have to change before evaluating a prototype model.

 

If you contact to below my e-mail address or let me know your e-mail address,

I can send the customer information.

I’m looking forward to hearing from you.

 

[my e-mail address]

Kanemaru-h@clv.macnica.co.jp

 

I’d greatly appreciate your verification.

 

Regards,

Kanemaru

Hi Kanemaru,

If the customer is going to use 10GBASE-KR mode, they just need to change the HS_PLL_MULT[3:0] to '1100' (x16.5), in this case the device is going to perform Auto-Negotiation and Link Training, if the these featured are no needed please disable them.

Regards,

Luis

Hi Luis-san,

 

Thank you for your prompt reply.

I understand that the register except " HS_PLL_MULT[3:0] " is a default.

Is my understanding correct?

 

> if the these featured are no needed please disable them.

 

Regards,

Kanemaru

Hi Luis-san,

 

Thank you for your kind support.

I confirmed that they don’t use the interface with SFP+ optical modules.

So, I suggest the default (except HS_PLL_MULT) to our customer.

 

Regards,

Kanemaru

Great! Please let me know if they have issues to link-up the device.

Regards,
Luis

Hi Luis-san,

Thank you always for your kind support.

I will contact you when I get new information.

Regards,

Kanemaru