TUSB1211: TUSB1211 Min Output Delay Time (TDD, TDC)

Hello,
Sorry for the delay, I will look for this information, can you give me some background about why do you think the failures are related to the delay time?
Also, can you elaborate more on your set-up?
Regards

We have a design that uses an Altera Cyclone V SOC processor with a ULPI interface connected to a TUSB1211.  We are seeing some units suffer periodic failures when running stress tests on the interface (e.g., running iperf via RNDIS, or running MD5SUM on large files stored on a USB stick, etc.) that appear to be corruption on the ULPI bus (the linux kernel driver reports unexpected packets / data received from the bus, or host requests are not acknowledged correctly).  

We can impact the failure rate with the following actions :

1.  Changing the configuration from using 26 MHz input reference clock (TUSB1211 sourcing 60 MHz on ULPI) to using an external 60 MHz clock (TUSB1211 receiving the 60 MHz on ULPI).  

2.  Replacing the TUSB1211 (with another TUSB1211).

3.  Modifying temperature (heating or cooling the unit).

The problem is presenting as though there is a marginal timing issue on the ULPI bus, and we are looking at the setup and hold time margins for transfers (in both directions) on the bus.  This is the reason for my post.  We can't do hold analysis on transactions from the TUSB1211 to the controller without the minimum output delay time.

We have tried looking at the clock jitter (and have tried a couple of different clock sources, some MEMs based, some Quartz based) and have not found any noticeable sensitivity to the clock technology.

-Mike

Hi,
Can you tell me the hold and set up minimum time of your FPGA?
Regards