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TFP410: Switching input clock issue

g.f.
Guru 15520 points
Part Number: TFP410

Hi,

I have a question about TFP410PAP.

My customer are having a problem with TFP410.
In their custom board, clock input for TFP410 is 40MHz or 66.66MHz.
The input clock can be switched(40MHz or 66.66MHz).
After switchig the input clock from 40MHz to 66.66MHz during system are running,
an output clock from TFP410 will be disordered(clock frequency will be about 80MHz) a few second to several minutes later.
(After this issue occur, the output clock will return to 66.66MHz)

When this problem occur, the connected monitor will be blackout for a moment.

Have anyone heard or had same issue using TFP410?

best regards,
g.f.

  • 0
    Guru 15520 points
    Hi,

    I have additional question related to above post.

    To avoid above issue, I'm suggesting to turn off the input clock before switching the clock from 40MHz to 66.66MHz.
    And then turn on the clock after switching to 66.66MHz.
    Because I guess this issue are related to TFP410 PLL lock and the PLL will be restarted and locked by turning off & on the input clock.

    If this is true, how long should they turn off the input clock?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Intellectual 2915 points
    Hi g.f,

    This may require to follow the PLL lock sequence to ensure PLL is in locked state. We will send you an update by next week.

    Dennis
  • 0 in reply to g.f.
    TI__Guru* 76130 points
    Hello,
    The TFP has a series of different PLLs in order to cover the whole frequency range, it is possible that these two frequencies are handled by different PLLs, however, it shouldn't take "seconds" to switch, the switching should be in the order of " hundreds of ms".
    How is this frequency change occurring at the TFP's input?
    Is the CLK going static low and then the new frequency or is it changing like in a "frequency modulation" ?, if that is the case then the TFP may be switching between many different PLLs.
    Regards
  • 0 in reply to Elias Villegas M.
    Guru 15520 points
    Hi Elias,

    Thank you for the reply.

    In my customer's board, the input clock are provided from FPGA to TFP410.
    Changing the clock from 40MHz to 66.66MHz are done by selector inside the FPGA.
    And there are no wait between changing the clock.

    They are planning to gave 10ms or more wait between changing the clock as follow:
    /////////////////////////
    1.providing 40MHz input clock
    2.stop input clock for 10ms or more
    3.start providing 66.66MHz
    //////////////////////////
    We don't know 10ms are enough.
    So, if there are any spec of wait time for TFP410 when changing the clock, can you please tell us?

    Or if giving the wait are meaningless,
    could you please give us an advise what is the best way to change the input clock for TFP410?

    Also, my customer are requesting following specification of TFP410.
    - PLL Reset specification
    - PLL power and clock startup sequence
    We checked the TFP410 datasheet, but there was no information.
    Are there any information?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 76130 points
    This issue is being handled with the field applications engineer, please contact him.