TLK10031: About recommended registers setting for 10GBASE-KR

Hi Kanemaru,

Attached you will find an application note with some useful information for the EQ of the device. In my understanding customers application is going to interface with SFP+ optical module, in this case the procedure to initialize the device is as follows:

1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)
2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).
3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
4. Disable link training by writing 16’h0000 to 0x01.0096
5. Write 16’h03FF to 0x1E.8020.  This allows the link settings that would normally be configured through KR training to be configured manually instead.
6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004.  For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.  This can be a starting point, but you may need to do some BER testing to optimize the values.
7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.

Sometimes the procedure to equalize the device is a little exhaustive, but this process needs to be performed manually (adjusting HS_SERDES_CONTROL_2 & 3).

4477.TLK10034_link_training_app_note (10).doc

Thanks,

Luis