Hi,
We are using only deser module from the(SN65LV1224B) TI chip. Serialiser (Inside Xilinx chip) is developed by us.
We are sending 10 bits of data with a Start and Stop Bits from the serialiser i.e. total 12 bits from the serialiser.
We are sending SYNC Pulses of 1111100000 to the deserialiser, to get the SER_LOCK condition to happen.
From this formula ---Serial data rate (Mbps) = 12 x REFCLKFrequency (MHz), from Ti community,
We are calculating SER_REFCLK=100mbps/12 => 8.33333 MHZ and we tried with SER_REFCLK= 10 MHZ also
We are unable get the SER_LOCK = 0. The deseraliser is not locking to the incoming frequency.
Sometimes The SER_LOCK is happening and going i.e. not stable.
Can you Please suggest , to get the SER_LOCK condition to happen.
