DP83867E: DP83867 about the schematic questions

Hey Mickey,

Full disclosure, Ethernet isn't my area here at TI but I have used this chip for both SGMII and RGMII successfully, I just stumbled across this. If this answers your question please verify the answer. With that out of the way, let's get you some answers!

Mickey Zhang said:

Q1:  The datasheet shows"For SGMII Mode 4 strap, TI recommends using Rhi = 4 kΩ and Rlo = 10 kΩ on RX_D0 and RX_D1 , RX_D2 and

RX_D3." 

The reason this line is here is because the RX_D0 and RX_D2, pin 33 and 35 respectively, are shared with the SGMII equivalent of Tx and Rx. However, these 4-level strap pins aren't responsible for SGMII enable, they handle the PHY addressing. The catch here is that RGMII uses single ended signals where as the SGMII mode uses differential pairs. Because of this, the straps the designer uses for determining the address can be anything. In RGMII, this is no problem since each RX_D"n" pin is independent of each other, but in SGMII this bias will cause impedance mismatching between the differential pairs and the signal will see deterioration from reflections. Now, bringing it back, because of this shared pin layout, the designers left RX_D1 and RX_D3, pins 34 and 36 respectively, as non-strap pins so that the signals can be impedance matched for SGMII mode.

To sum up, strap those pins however you want based on the address assignment you want for the PHY. Low and high is a bit unclear here since there are four levels but just use the errata they mention on four level straps.That note is only to be acknowledged if you are impedance matching the lines for SGMII differential mode operation.

Mickey Zhang said:

Q2:  How to deal with the GPIO_0 pin and GPIO_1 pin? floating?

Are you using the GPIO? These are four level straps too for selecting RGMII clock skew. To be clear, the purpose of the straps is to add DC bias for adding additional capability to the part, so you can use the internal default strapping of 00 and still send data on the line if that operational mode works for you. The only time you are required to strap is if the default 00 doesn't work for your purposes or impedance matching (check the strap config tables). I say required because I am paranoid and like ensuring that there is no chance my levels will change on me, so I include external straps on everything pretty much. The headache saved is well worth the one 0402 strap cost and space IMO.

Anyway, I assume you don't need them since you want to know if you can leave them floating. These are tied internally to level 00 or GND, so if you don't need to adjust skew and not using them at all for GPIO purposes (i.e. sending no data) then tie to weak external pull down (~10k-100k). 

Mickey Zhang said:

Q3: Can only use LED_0 pin,not use LED_1pin and LED_2 pin in the RGMII mode ? If it is ok, then  LED_1pin and LED_2 pin can be floating?

Again, are you wanting to use these LEDs for there intended purpose of indcating links? All three will work in either mode, it's just that they have additonal features provided via straps if you don't want the default 00 mode. (HINT: You will want to use all three I'd bet, just not their additional four level strap options).

When you strap the LED_0, pin 47, you are choosing between SGMII enabled or disabled, with no external strap it will automatically revert to the default of mode 00; RGMII (The mode you want). Now that handles which SGMII mode, also the "Mirror" setting that you are using, is used and will complete the biasing of LED_0. Again, in this case if you want "mirror" disabled too, then you aren't required to have any strapping, but I recommend a weak pull to GND anyway. 

Follow the same procedure for LED_1 and LED_2. Again, I recommend that if you leave the default mode 00 strap with a weak external pull to GND anyway.

Mickey Zhang said:

Q4:  Are the JTAG pins pins needed to use? If not ,then the JTAG pins can be floating?

Do you need to do VIT testing or boundary scans, it sounds like no. In this case, then the input JTAG pins should be GNDed and the output (TDO) can be left floating. If you haven't picked up on it yet, I recommend that you GND it though via a weak external pull to avoid spurious potentials. Additionally, if this is a test board, I would add some 100mil headers on there in case you do want that functionality later or just want to learn JTAG (Fun times)!  

Mickey Zhang said:

Q5: There are only the DP83867ERGZ-R-EVM Altium file on our website. The customer needs the PADS file or the Allegro file.

Do we have the  PADS file or the Allegro file for the DP83867ERGZ-R-EVM?

To my knowledge we don't. However, just google, "Convert Altium files to Cadence" and you should find some free and paid ways to make the conversion.

Best Regards,

Nick

If this answered your question, then please hit the green "Verify Answer" button below! If you have any questions or concerns just let me know.