Hi, Expart.
Please help us.
My customer's questons are below.
1)
We saw the Figure.1.(Below chart)
Figure.1 is the sequence of power up timing. (Document#: SNLS484E)
Figure.1 shows input XI clock before VDD power on.
Should we need to input XI clock signal before VDD input?
2)
We don't know about sequence rules when power off.
Don't we have to think about something to special sequence?
Don't we have to care about sequence rules when power off?
3)
We know DP83867 is capable of operating with two or three power supplies.
We will operating with two-supply.
What should we be careful with operating with two-supply?
Is there nothing to worry about?
4)
Is the DP83867I only receiving 125 MHz from the external clock and output it?
Can the DP83867I generate 125 MHz independently and output it?
Best Regards,
Ryuji