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TPS65986: Debug accessory mode and GPIO pin assignments

Jonny Hall
Prodigy 65 points

Part Number: TPS65986

I am working on a USB-C design, with the TPS65986 currently penciled in, although I am willing to change to the TPS65982 if necessary.

Requirements:

  • Power source 5V/3A (available through internal PP_5V0 power path on any TPS6598x device)
  • Power sink 27W profile minimum (9V/3A min, 15V/3A max) (available through internal PP_HV on any TPS6598x device)
  • Dual role data port supporting USB 2.0, USB3.0 + 1-lane DisplayPort, or 2-lanes DisplayPort only alternate mode (using HD3SS460 in slightly non-standard config for high-speed signal mux)
  • Desirable: Support Debug Accessory Mode with pass-through of 2-4 internal signals (console UART etc.) for factory test procedure.

Since my power requirements can be met using the internal power paths on any part, and I don't require thunderbolt support, I originally thought that the TPS65986 would be appropriate.  However, I am confused by the GPIO and debug configurations:

-The pinout documentation of both parts lists GPIO0-8, RESETZ, BUSPOWERZ, MRESET, and DEBUG1-4, but in the pinout table refers to all of these pins as GPIOs.  Additionally, the TPS6598x Application Customization Tool (version 3.4) has a section under Shared Device Settings -> GPIO Event Map where it appears that these I/O are all flexible.  However, it appears that GPIO4 and 5 are specifically defined to relate to displayport HPD.

Question 1: Which GPIO pins have specific definitions that cannot be changed by software configuration? 

-The TPS65986 mentions the port data multiplexer, debug accessory mode, and has 4 pins labelled DEBUG1-4, however in the datasheet on page 47 it does not actually show the DEBUG pins as capable of routing through the mux in debug accessory mode. Moreover, the application configuration tool doesn't show any configuration for this mode.  The TPS65982 does show DEBUG1-4 (as well as two additional pins, LSX) as routing through the mux (datasheet page 52) but provides little additional information on the configuration of debug accessory mode. The application configuration tool also does not show any configuration options for this.

Question 2: Does the TPS65986 support pass-through of system signals using debug accessory mode? If so how is it configured? If not, does the TPS65982 support this and how is it configured?  Would there be other design changes required to move from -6 to -2?

Question 3:  Can the TPS6598x devices drive their GPIOs such that the HD3SS460 AMSEL and EN pins can be driven to the mid level / floated?  My current mode mapping is for USB 3 + 1-lane DP [AMSEL=H, EN=H] and for 2-lane DP only [AMSEL=M, EN=M].  This configuration is because my host processor has two transceiver channels available, one of which is DisplayPort lane 0 and the other of which is either USB3 or DisplayPort lane 1.

Thanks!

  • 0
    TI__Mastermind 36756 points
    Hi Jonny,

    Question 1: Which GPIO pins have specific definitions that cannot be changed by software configuration?
    GPIO4, GPIO9, GPIO10, and GPIO11 cannot be changed by software configuration

    Question 2:
    The TPS65982 device enters Debug Accessory Mode when it detects the states of both CC pins at SRC.Rd range (that is, the debug accessory identifies itself by presenting a resistance to Rd on both CC and VCONN pin of the USB Type-C plug).The TPS65982 device configures the USB Type-C port multiplexer. The TPS65982 device requires no checks for proper orientation of the debug accessory. The user is assumed to be responsible for providing the proper orientation of the debug accessory. The system port signals, UART_TX and UART_RX, are rerouted by the digital crossbar inside the digital core. The UART_TX and UART_RX signals are level shifted and buffered, routed through the cross bar mux, and level shifted to the USB Type-C port signals C_USB_BP and C_USB_BN, respectively. In addition, the system port signals USB_RP and USB_RN are routed as analog signals to the USB Type-C port signals C_USB_TP and C_USB_TN, respectively. Lastly, the system port signals SWD_CLK and SWD_DIO are routed as analog signals to the USB Type-C port signals SBU1 and SBU2, respectively.

    Question 3:
    The TPS6598x devices will either drive the signals high or low when configured to those events.

    Thank you,
    Eric
  • 0 in reply to Eric Beljaars
    Prodigy 65 points
    Hi Eric,
    Thanks for the quick reply!

    To clarify on question 2: The TPS65982 datasheet pg. 52 shows the port data crossbar mux configuration, and in addition to the system UART_TX/RX, USB_RP/RN, and SWD signals you mentioned, it also shows DEBUG1-4 and LSX_P2R/R2P. Are these signals available to be connected to port pins through the mux on either the 65982 or 65986, and if so how is this configured?

    Thanks!
    -Jonny
  • 0 in reply to Jonny Hall
    TI__Mastermind 36756 points
    Hi Jonny,

    The DEBUG 1-4 pins and LSX_P2R/R2P are not available in the debug accessory mode to be connected to port pins. Only the UART_TX/RX, USB_RP/RN, and SWD signals are supported with the Debug accessory mode.

    Thank you,
    Eric