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DP83848Q-Q1: compliance test for 100Base-TX

K.Yaita
Guru 29710 points
Part Number: DP83848Q-Q1

Hi Team,

I found the following thread about compliance test for 100Base-TX and would like to ask a question.
https://e2e.ti.com/support/interface/ethernet/f/903/p/491013/1773271?tisearch=e2e-quicksearch&keymatch=Pseudo#1773271

----------------------------------------------------------------------------------------
Additional register sequences for 100Base-TX output signaling
----------------------------------------------------------------------------------------
To output a Pseudo-random packet in 100Mbps:

  1. Force 100M, full duplex (write 0x2100 to address 0x00)
  2. Force 100M good link (write 0x0120 to address 0x16)
  3. Start BIST transmission of PSR9 pattern (write 0x1to bit 8 of address 0x19)


Regarding above content, could you tell me which test item (test situation) that requires "To output a Pseudo-random packet in 100Mbps"?

Best Regards,
Yaita / Japan disty

  • 0
    TI__Mastermind 19780 points
    Hi Yaita-san,

    The pseudo-random packet generator is used for debugging links. PRBS is not necessary for compliance tetsing.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Guru 29710 points

    Hi Rob-san,

    Thank you for your kind support.
    May I ask an additional question?

    The following thread shows "address 0x1F" however it is reserved register according to DP83848Q-Q1 datasheet.
    -----------------------------------------------------------------------
    http://e2e.ti.com/support/interface/ethernet/f/903/p/491013/1773271?tisearch=e2e-quicksearch&keymatch=Pseudo#1773271

    ANSI X3.263-1995: 9.1.2.2 Differential Output Voltage, 9.1.4 Signal Amplitude Symmetry, 9.1.3 Waveform Overshoot
    Enable a 14T/6T pattern that alternates between a positive 14T pulse and a negative 14T pulse with 6T between each positive and negative pulse.
    To configure the 14T/6T pattern:
    1.Force 100M (write 0x2100 to address 0x00)
    2.Enable 14T/6T pattern (write 0x2407 to address 0x1F)
    3.After testing, disable 14T/6T pattern (write 0x2400 to address 0x1F)
    -----------------------------------------------------------------------

    Should I regard the address 0x1F register as it is prepared for only compliance tetsing?

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Mastermind 18425 points
    Hello Yaita-san,

    Yes, please use register 0x1F for compliance only. It is necessary to disable 14T/6T pattern after testing (point 3 above) to enable normal operation.

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Guru 29710 points

    Hi Aniruddha-san,

    Thank you for your support.

    Is it possible to disclose the detail register content of 0x1F register?
    My customer wants to know bit assignment and explanation.

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Mastermind 18425 points

    Hello Yaita-san,

    Apologies for the delay on getting back on this. The register contains information which is not approved for public release, so we will not be able to disclose the bits. From a complaince point of view, please use only the values listed in the post above and disable the pattern after the test is completed.

    -Regards,

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Guru 29710 points

    Hi Aniruddha-san,

    Thank you always for your support.
    I would like to ask two additional questions.

    1)
    My customer found the following "14T/6T pattern" and "2T pattern" couldn't be disabled (stopped) after writing 0x2400 to address 0x1F.

    So he did power cycling to disable at the moment.
    Is it possible case for DP83848Q-Q1?
    ----------------------------------------------------------------------

    ANSI X3.263-1995: 9.1.2.2 Differential Output Voltage, 9.1.4 Signal Amplitude Symmetry, 9.1.3 Waveform Overshoot

    Enable a 14T/6T pattern that alternates between a positive 14T pulse and a negative 14T pulse with 6T between each positive and negative pulse.

    To configure the 14T/6T pattern:

    1. Force 100M (write 0x2100 to address 0x00)
    2. Enable 14T/6T pattern (write 0x2407 to address 0x1F)
    3. After testing, disable 14T/6T pattern (write 0x2400 to address 0x1F)

    ANSI X3.263-1995: 9.1.8 Distortion (Duty Cycle)

    Enable a 100M 2T pattern (+1, +1, 0, 0, -1, -1) for DCD testing. The ANSI TP-PMD tests specifies a pattern with 16ns widths, hence two bit times on the wire.

    To configure the 2T pattern:

    1. Force 100M (write 0x2100 to address 0x00)
    2. Enable 2T pattern (write 0x2406 to address 0x1F)
    3. After testing, disable 2T pattern (write 0x2400 to address 0x1F)

    http://e2e.ti.com/support/interface/ethernet/f/903/p/491013/1773271?tisearch=e2e-quicksearch&keymatch=Pseudo#17732
    ----------------------------------------------------------------------

    2)
    My customer wants TI to confirm the waveforms (14T/6T pattern, 2T pattern, etc) they captured are expected or not.
    He plans to outsource compliance testing after the confirmation.

    Could you send me the email to the following address if feasible?
    I would like to send the waveform capture to you.
    yaita-k@clv.macnica.co.jp


    Best Regards,
    Yaita / Japan disty

  • 0 in reply to K.Yaita
    Guru 29710 points

    Coud you kindly support for the post above?
    Your support would be apprecitated.

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Mastermind 18425 points

    Hello Yaita-san,

    Power cycle or Reset will cause the PHY to return to its default state. For compliance testing, power cycle and reset are both ok to use.

    I will reach out to you on E2E with a private message. You can share the photos there.

    -Regards,

    Aniruddha