DP83848Q-Q1: compliance test for 100Base-TX -(2)

K.Yaita

Part Number: DP83848Q-Q1

Hi Team,

The following thread describes about compliance test for 100Base-TX.
https://e2e.ti.com/support/interface/ethernet/f/903/p/491013/1773271?tisearch=e2e-quicksearch&keymatch=Pseudo#1773271

In the following each test item, I believe DP83848Q-Q1 generates test pattern by itself and it isn't required to be gererated by external microprocessor.
Is my understanding correct?

ANSI X3.263-1995: Annex J AOI Template, 9.1.6 Rise Time, 9.1.6 Fall Time, 9.1.6 Rise Fall Symmetry, 9.1.9 Transmit Jitter
ANSI X3.263-1995: 9.1.2.2 Differential Output Voltage, 9.1.4 Signal Amplitude Symmetry, 9.1.3 Waveform Overshoot
ANSI X3.263-1995: 9.1.8 Distortion (Duty Cycle)
ANSI X3.263-1995: 9.1.5 Transmitter Return Loss, 9.1.5 Receiver Return Loss

Best Regards,
Yaita / Japan disty

over 8 years ago

0 K.Yaita over 8 years ago

Guru 29720 points

May I have your comments?

Best Regards,
Yaita

0 Geet Modi over 8 years ago in reply to K.Yaita

TI__Mastermind 26320 points

Yes, please follow the steps mentioned in the e2e thread to configure DP83848 for various tests.

Regards,

Geet

0 K.Yaita over 8 years ago in reply to Geet Modi

Guru 29720 points

Hi Geet-san,

Thank you for your support.
May I ask an question about 14T/6T pattern?

https://e2e.ti.com/support/interface/ethernet/f/903/p/491013/1773271?tisearch=e2e-quicksearch&keymatch=Pseudo#1773271
>Enable a 14T/6T pattern that alternates between a positive 14T pulse and a negative 14T pulse with 6T between each positive and negative pulse.
Is the following pattern correct for 14T/6T pattern?
(+1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, +1, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)

Best Regards,
Yaita

0 Geet Modi over 8 years ago in reply to K.Yaita

TI__Mastermind 26320 points

Your understanding is correct.

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DP83848Q-Q1: compliance test for 100Base-TX -(2)