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DP83822HF: RX_CLK and TX_CLK become half of XI frequency

Yaoting Yang
Intellectual 780 points
Part Number: DP83822HF

Hi,

The following is my bootstraps setting,

COL: MODE2;

CRS: MODE1;

RX_ER: MODE1

The rest ones are using Default.

XI = 25MHz, I got RX_CLK and TX_CLK 's outputs of 12.5MHz. Any other settings have be ignored? Need your help, 

Appreciate!

Yaoting Yang

  • 0
    TI__Mastermind 18425 points
    Hello Yaoting,

    Can you read the PHY registers when it is in this state? Please read 0x00, 0x01, 0x09, 0x0A, 0x0B, 0x0F, 0x10, 0x11, 0x17, and 0x19.

    Would it be possible to share your schematics?

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Intellectual 780 points

    Hi Aniruddha,

    Thanks for your helps.

    Here are the register power-up values:

    0x00=0x2100

    0x01=0x7849

    0x09=0x0

    0x0a=0x2500

    0x0b=0x100b

    0x0f=0x0

    0x10=0x4

    0x11=0x108

    0x17=0xc1

    0x19=0x0

    Then, I changed the following register values:

    0xa -->0x4000

    0xb -->0x1000

    0x17 -->0x41

    Now i got the correct MII bus clocks they are 25MHz. ox17 register was effective. It looks like the default settings are RMII @50MHz not the MII @25MHz. Why? Could my bootstraps settings be wrong?

    Another problem is that there are not any TD_P/N signals seen. Need your helps. I've attached my schematic for your check. The parts with the values of UI are not populated.

    Appreciate!

    Yaoting

    dp83822.pdf