DP83867CS: SGMII latency

Hello

Is there anyone who can help me please?

It looks like the DP83867E device has better timing for the SOF so I'm more interested in that.

Can anyone tell me the latency min and max for the SGMII interface please?

Thanks

Mark

Hi

I was hoping to use the reception of a packet to trigger something in my system.

I send a packet at a precise time, but then it needs to go through the Tx PHY through the SGMII port, out the MDI port, over the wire, then into the Rx PHY's MDI port and out of the SGMII port. I need to know the latency for Tx SGMII - MDI and Rx MDI - SGMII. I am not too concerned about the total time, but the difference between max and min gives me a jitter value that is important to me.

I know that with the SFD flags I can save the latency of the Rx PHY, this is very interesting for me for this particular chip.

The specs show a nominal time for Tx RGMII to MDI and Rx MDI to RGMII but not a min max. For me the SGMII is better because I have very few pins to play with on the MAC FPGA.

Can you help?

Thanks

Mark

Hi Mark,

I am working on getting the expected latency information. This is not something that we have released in the datasheet so we will have to take the discussion offline.

-Regards,
Aniruddha