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DS110DF111: register for input signal

TS Yang
Genius 4800 points
Part Number: DS110DF111
Other Parts Discussed in Thread: DS125DF111

Hello,

We are considering applying TI's DS110DF111 2-ch retimer for our network application, and have a question as below.

Is there a register that can check if the incoming signal is enough to recognize for retimer?

The cause of inquiry is to check if there is a case where CRC packet loss may occur due to CDR lock when the eye pattern of input signal pattern is bad and the bad signal is restored and output.

thanks,

TS

  • 0
    TI__Mastermind 19235 points

    Hi TS. The DS125DF111 has input signal detect function. The signal detect circuit is asserted when valid input signal is present i.e. when the detected input signal peak voltage exceeds some defined minimum threshold. Channel register 0x01 bit 0 is the Signal Detect Interrupt pin.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Genius 4800 points
    Hello,
    I know that the loss is related to the presence or absence of the signal. Is there anything that can be confirmed with the minimum signal level or the like to restore the normal eye signal to the input signal?
  • 0 in reply to TS Yang
    TI__Mastermind 19235 points

    Hi,

    The TI retimer actively measures the horizxontal eye opening (HEO) and vertical eye opening (VEO) observed after the Rx equalization stages and before the CDR. These values are used as part of the EQ adaption process. Moreover, meeting a minimum threshold for HEO and VEO is acriteria for gating CDR lock. If desired the user may adjust the HEO and VEO lock thresholds via I2C channel register 0x6A:

    　

    Address

    (Hex)

    BITS

    DEFAULT VALUE (Hex)

    MODE

    EEPROM

    FIELD NAME

    DESCRIPTION

    6A

    7

    0

    RW

    Y

    VEO_LCK_THRSH3

    VEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.

    6

    0

    RW

    Y

    VEO_LCK_THRSH2

    5

    1

    RW

    Y

    VEO_LCK_THRSH1

    4

    0

    RW

    Y

    VEO_LCK_THRSH0

    3

    0

    RW

    Y

    HEO_LCK_THRSH3

    HEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.

    2

    0

    RW

    Y

    HEO_LCK_THRSH2

    1

    1

    RW

    Y

    HEO_LCK_THRSH1

    0

    0

    RW

    Y

    HEO_LCK_THRSH0

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Genius 4800 points

    Hi TI,

    thanks for your answer.

    In order to improve the packet loss situation, I changed the structure to "switching chip ← retimer ← connector ← repeater ← SFP + optical module" structure, but the number of times of CRC occurrence or eye monitoring of retimer seems to be getting worse.

    Repeater settings were changed by changing the VOD, EQ, and De-emphasis values. Please let me know if there's any other points to check.

    thanks,

    TS

  • 0 in reply to TS Yang
    TI__Mastermind 19235 points

    To be able to troubleshoot I will need more info related to your link.

    What is the estimated insertion loss at ~5GHz in between the retimer and repeater, and also in between the repeater and SFP+ electrical output pins?

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer