DP83822I: Reset Timing

Hiroshi Katsunaga

Mastermind 6480 points

Part Number: DP83822I

Hello,

My customer has a question about DP83822I.

[Q]

Is it necessary to deassert (logic high) RESET_N pin before assert (logic low) it in H/W Reset timing ?

Please refer to the following figures.

Is it acceptable with the following timing ?

Best Regards,

Hiroshi Katsunaga

over 8 years ago

0 Ross Pimentel over 8 years ago

TI__Mastermind 23675 points

Hi Hiroshi,

You do not need to have RESET HIGH prior to pulling it LOW.
The reason why I made the original diagram with the RESET HIGH is that after power-up, RESET will go HIGH because there is an internal pull-up.
If the user wants to put the device in reset they will need to pull it LOW. I also had the RESET HIGH because it helps me show the customer how T1 is defined.

Kind regards,
Ross

0 Hiroshi Katsunaga over 8 years ago in reply to Ross Pimentel

Mastermind 6480 points

Hi Ross,

Thank you for your fast response.
OK, I understood your all comments.

Thank you for your cooperation.

Best Regards,
Hiroshi Katsunaga

Interface

Interface forum

DP83822I: Reset Timing