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DP83822I: DP83822 Latency

Pascal REGACHE
Prodigy 240 points
Part Number: DP83822I

Hello,

I am interested in PMD to RMII transmit and receive latency numbers (there is another thread on that subject, but the answer has been kept private).

So far I have been assuming DP83848 numbers given in teh product datasheet and SNLA076A document (timing T2.26.4 and T2.27.5)

Can I get an update on these numbers for the DP83822 ?

Also, the DP83822 features the "RMII Recovered Clock Async FIFO Bypass" bit in RCSR regsiter. How the setting impacts the receive latency (latency with bit set and clear) ?. According to the datasheet, the bit is set by default. This is is strange given that the clear state (0) is described as "normal operating" mode. Is this a mistake ? I am running in RMII slave mode, so I guess this bit shall be cleared. Correct ?

In the same register, bit  "RGMII TX Synced"  to optimize transmit latency. Is there a similar bit available in RMII mode as running the MAC and the PHY out of the same reference clock would maybe allow some latency optimisation.

Thanks, Best regards

Pascal

  • 0
    TI__Mastermind 23675 points
    Hi Pascal,

    I am sorry for the delay. It was not our intention to let this stay open so long.

    In regards to your questions:

    1. Typical RMII TX latency is 130ns
    2. Typical RMII RX latency is 270ns
    3. You are correct, there is an error in the datasheet. RMII Clock Async FIFO Bypass should be 0b0 by default.
    4. By enabling it, you reduce your variability on the receive path and reduce your latency. You need to use the RX_CLK pin for this mode and feed it to the MAC.
    5. There is no TX Sync option for RMII operation.

    Best regards,
    Ross
  • 0 in reply to Ross Pimentel
    Prodigy 240 points

    HI Ross, thanks for the answer.

    About point 3 and "RMII recovered clock async FIFO bypass", we have experimentally verified that the bit is set after reset.

    So I do no understand your answer. The datasheet is correct with respect to the silicon and, if the description is correct, then RMII slave operation requires to clear that bit.

    Am I correct ? Please confirm.

    Pascal

  • 0 in reply to Pascal REGACHE
    TI__Mastermind 23675 points
    Hi Pascal,

    I am sorry for the confusion here.
    RMII recovered clock async FIFO bypass is not enabled by default.
    A '1' means normal operation and '0' means FIFO bypass.

    Best regards,
    Ross