This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90CR286: DS90CR286: Clock stuck at "1" on the CMOS side of the receiver

Part Number: DS90CR286
Other Parts Discussed in Thread: DS90CR285

Dear TI community,

I have the following problem.


I am trying to connect two boards, one of which has DS90CR285 transmitter and another - DS90CR286 receiver rescpectively. On the first board there are only 14 bits of data fed to the input of the DS90CR285, therefore only two differential channels are used (TxOUT2 and TxOUT3). When I connect these boards with the UTP cable, I can see with the scope that on the differential inputs of the DS90CR286 there is a presence of the running clock going form the first board and through the cable to the receiver. But on the CMOS/TTL side of the DS90CR286 clock line stuck at the logic "1" level. At the current moment, I can't figure out why this is happening. I've checked the cable, in case I've messed up with the data/clock pairs and feed clock line with the data, but it seems that all is OK.

What probably could cause such behavior of the receiver? Is this matter to which data inputs of the DS90CR286 I should wire outputs of the DS90CR285 in case where only two channels are used?
I would be very grateful if you have any suggestions where I should look to solve this matter.

Best regards, Igor.

  • Hi Igor,

    Do you have all unused inputs at the TxIN of the transmitter tied to ground, and all unused outputs at the RxOUT of the receiver floating?

    Regards,
    I.K.
  • In regards of the transmitter, all unused inputs are tied to ground. But in case of receiver all outputs are connected to the FPGA (Altera Cyclone II).

    These pins were reserved in case we'll need them in the future, and I saw similar setup where everything worked well. Should I check that on the receiver side all unused pins of the FPGA are set as "inputs tri-stated", or it doesn't matter in this case? I didn't design this receiver board, so I need to talk with the board developer and clarify these details.

    Also I found that PWR_DWN pin of the DS90CR286 was left floating. I begin to suspect that this pin is the source of my problem. Does PWR_DWN circuitry have some internal pull-up/pull-down?

  • Hi Igor,

    Sorry for the delayed response. I cannot say much about FPGA settings, but I checked with others and it looks as though there is an internal pulldown on the PWR_DWN pin.

    Regards,
    I.K.
  • Hi I.K.,
    I'd like to sorry for the delayed response too. I wasn't working during the weekend, therefore wasn't able to try to pull the PWR_DWN to the VCC of the DS90CR286 for the test.
    After the PWR_DWN pin was soldered to the VCC level with the wire, everything started to work as it should.
    Thank you for information and help!

    Regards,
    Igor.