It is not clear on the EVM how the P1 and P3 headers are pinned out - Please provide guidance so that we can identify each pin on the Headers and associate that to the EVM schematic
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It is not clear on the EVM how the P1 and P3 headers are pinned out - Please provide guidance so that we can identify each pin on the Headers and associate that to the EVM schematic
Hi Steve,
From the schematic, BOM, and picture of the EVM from this document: http://www.ti.com/lit/ug/sllu013/sllu013.pdf
I believe P3 is pinned out like so:
And P1/P2 are pinned out like so:
Regards,
I.K.
The datasheet output charateristic graphs (Figures 5 and 6) show a V-I curve that indicate an equivalent output impedance (from the slope of the curves) that is greater than the 5 ohms shown in the equivalent circuit. The impedance looks like ~ 33 - 50 ohms just by using the slope (depending on the output current). Please confirm.
Figures 5 & 6 of the datasheet show Vo characteristics from 0mA to > 60mA sourcing or sinking. However, the ABS max for Iout is shown a 12mA. Is it acceptable to load more than 12mA? If so why do Figures 5 and 6 suggest that it is ok to load beyond 12mA?