TMDS181: About max value of pin capacitance of SCL_SNK and SDA_SNK

Hi Kanemaru,

You can find this information in the datasheet's section 6.8 (Cbus), the maximum total capacitive load for each bus lines (DDC and local I2C pins) is 400pF.

Regards

Hi Moises-san,

Thank you for your prompt reply.

However, we would like to know the Parasitic capacitance of those pins(I guess that it is few pF).

Because, our customer needs this information to design.

Could you please let us know if you have any information?

Regards,

Kanemaru

Hi Moises-san,

Thank you for the information.

I understand. Thank you very much.

Regards,

Kanemaru

Hi Moises-san,

I've got an additional request from our customer .

Could you please let us know if you have a histogram of the Parasitic capacitance(around 10pF)?

Because, they would like to know the Variation of this spec.

If you contact to below my e-mail address or let me know your e-mail address,

I can send the customer information.

I’m looking forward to hearing from you.

[my e-mail address]

Kanemaru-h@clv.macnica.co.jp

Regards,

Kanemaru

Hi Kanemaru,

I'm looking for this information, I will come back when I have suitable data.

Regards

Hi Moises-san,

Thank you for your kind support.

I’m looking forward to hearing from you.

Regards,

Kanemaru

Hi Moises-san,

Thank you for your response.

In order to make the set compliant to HDMI specifications, the maximum

capacitance value of SCL_SIK and SDA_SNK pins are mandatory.

Please understand this request and provide an estimated maximum

capacitance value of these pins with reasonable guard band.

I’m sorry to trouble you, but I would really appreciate it if you could confirm.

Regards,

Kanemaru

Hi Kanemaru,

I'm still waiting for a response from my team.

In boards without a level shifter to isolate the capacitance, is common that this test fails because of all the devices on the bus.

A level shifter is necessary most of the times, in this case, only the level shifter and the TMDS181 are measured by the test, even the TMDS181 can be placed after the level shifter to reduce the capacitance. In this case, I haven't seen failing boards.

Regards

Hi Moises-san,

Thank you for your kind advice.

However, they need an estimated maximum capacitance value.

I’d greatly appreciate your verification.

Regards,

Kanemaru

Hi Moises-san,

Thank you for your kind support.

What do you think about the present situation regarding this matter?

I’d greatly appreciate your verification.

Regards,

Kanemaru