DS90C387: single-to-dual LVDS display driver

tracemhos

Part Number: DS90C387
Other Parts Discussed in Thread: AM5728

I have a dual-channel LVDS display from Sharp - part # LQ185M3LW01. I believe I have the RGB bits mapped correctly to the DS90C387 (R0 to pin R10, B0 to pin B10, and G0 to pin G10). I also believe we have the clock and Hsync / Vsync / DE signals correct, however we can't get anything to display onto the screen (not even a garbled image). I'd like to confirm the status of the control pins, here is what I assume is correct:

PRE: 100k pullup

PLLSEL: 0 ohm pullup

R_FB: 0 ohm pullup

R_DE: 0 ohm pullup

Dual: 10k/10k resistor divider

Bal: 0 ohm pullup

We've been struggling to get anything to display at all, even a scrambled image, any help would be greatly appreciated. There are very few app-notes on how to properly configure a single-to-dual display even though its marketed as such.

over 8 years ago

0 tracemhos over 8 years ago

Prodigy 100 points

As a clarification, we are using the AM5728 sitara processor connected to the DS90C387 and cannot seem to get the system to work together. The display vendor is reviewing the signal timing and has suggested that the VOUTx_DE signal is not properly configured (period too short for a singe-to-dual configuration). We are trying to determine what else might need to be changed in the timing configuration as the hardware (display, cabling, DS90C387) all appear to be functioning properly but still nothing on the display

0 Ryan Hashimoto over 8 years ago in reply to tracemhos

TI__Intellectual 1635 points

Hi,
I will review your set-up listed above and provide a response shortly.
Regards,
Ryan

0 Ryan Hashimoto over 8 years ago in reply to Ryan Hashimoto

TI__Intellectual 1635 points

Hi,

I have reviewed your control signal configuration and it is correct for single-to-dual mode. Below are my comments regarding the control signals.
PRE: 100k pullup – minimal amount of pre-emphasis – What is your clock frequency, cable length, and cable type?
PLLSEL: 0 ohm pullup – tied to Vcc for auto-range – correct.
R_FB: 0 ohm pullup – Rising edge data strobe selected.
R_DE: 0 ohm pullup – are you referring to “R_FDE”? If R_FDE is tied high data is active when DE is high.
Dual: 10k/10k resistor divider – correct set-up for single-to-dual mode. A capacitor between “DUAL” pin and ground will help to stabilize the DC voltage level in a noisy environment.
Bal: 0 ohm pullup – tied to Vcc to enable DC Balance.

Have you connected an oscilloscope at the end of your cable to confirm the integrity of the LVDS signals prior to being received by the display?

Regards,
Ryan

0 tracemhos over 8 years ago in reply to Ryan Hashimoto

Prodigy 100 points

Ryan,

thanks for following up on this. We ended up discovering a hardware issue where the clock / rxin2 were swapped, but we also had a software issue that was finally resolved. We had been trying to adjust the timing parameters of the clock frequency / hsync / vsync to match the panel specifications knowing the clock frequency was being devided by 2, but trying to adjust all the parameters together was problematic. We finally discovered the "doubleclk" boolean and found that by keeping the parameters the same as the panel but doubling only the clock frequency resolved the issue.

panel-timing {
            clock-frequency = <74000000>;
            hactive = <1920>;
            vactive = <1080>;
            hfront-porch = <126>;
            hback-porch = <126>;
            hsync-len = <20>;
            vfront-porch = <17>;
            vback-porch = <17>;
            vsync-len = <11>;
            de-active = <1>;
            pixelclk-active = <1>;
            doubleclk;
        };

Appreciate the assistance!

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DS90C387: single-to-dual LVDS display driver