In document named "AN-1794 Using RMII Master Mode", Figure 7, it mentioned that DP83630's TX_CLK pin outputs 25MHz clock when work at RMII master mode. Unfortunately, I cannot find any words to support it in DP83630's datasheet.
In DP83630's datasheet, in section 3.4, it mentioned "For RMII Master mode, the device outputs the internally generated 50 MHz reference clock on this pin". It conflict with AN1794 obviously .
I think maybe AN-1794 has some typo error in Figure 7, and "TX_CLK" should be replaced by "CLK_OUT", although the "CLK_OUT" should be replaced by "TX_CLK".
Am I right?
